ARM AMBA AHB Notes:

The AHB bus has 2 phases, Address Phase and Data phase.

HREADY. Whats the fuss?

HREADY is an output signal from every slave, which is routed to every Master and every slave.
This means each slave will have 2 HREADY signals
HREADY_in and HREADY_out.

Address phase cannot be extended, hence all slaves must sample the address during
this time. The data, however, can be extended using the HREADY signal.

HREADY signal is both, input and output from Slaves.

Q. Why HREADY an o/p from slave?
A. HREADY is an o/p from slave so that it can extend the data phases if it needs more time.

Q. Why HREADY is an input to slave?




A. The Arbiter Grants a Master the bus on the Last clock cycle of the data phase of the previous Master,
because the arbiter keeps track of the number of transfers and it knows the burst size and all characteristics.
Say an INCR4 burst is currently ongoing by Master1 to Slave2. The data phase will be 4 clock cycles,
if the HREADY from Slave2 is always high.
The Dataphase will however be 5 clock cycles if say for example the Slave2 extends the DP3 into two
clock cycles say DP3_0 and DP3_1, HREADY being '0' in DP3_0.
In absence of HREADY being an input to slave, another slave in the system say Slave3, will
see its HSEL go '1' in DP3_0, and it will start responding in DP3_1, which will result in data corruption.
But Since HREADY is also availsble to this Slave3, it will come to konw that even when it has its HSEL go to '1'



The recommended default value of HREADY is '1'.

Q. When would a master sample 'hready'
A. Since 'hready' is only related to data phase, the Master would sample 'hready' at the N+1th edge, where N is the clock edge, at which it issued the data.


When a master is granted the bus and is performing a fixed length burst it is not
necessary to continue to request the bus in order to complete the burst. The arbiter
observes the progress of the burst and uses the HBURST[2:0] signals to determine how
many transfers are required by the master.


For undefined length bursts the master should continue to assert the request until it has
started the last transfer. The arbiter cannot predict when to change the arbitration at the
end of an undefined length burst


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