Multilayered AHB AHB Bus Matrix

AHB Multi Layered Bus Vs Normal Bus
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AHB Multi Layered Bus/Multilayer AHB/AHB Bus Matrix.

This page is about Multilayer AHB interconnect. It is different to traditional AHB bus where AHB HBUSREQ/HBUSGNT
signals were used to get hold of the common bus, and only 1 Master/Slave pair could interact at a given time.
If any master/slave pair is engaged in a transfer, all the other Master/Slaves has no choice but to wait.
This situation is addressed by a AHB Multilayered bus, where the arbitration takes place at the Slave port of the arbiter/bus.
The Multilayer AHB bus is also called AHB Bus Matirx (More on ARM AHB Bus Matrix can be found here)

Using this Multilayer concept (or using the AHB Bus Matrix as it is called by ARM),
Master M1 can interact with Slave S3, the other master say M2 can interact in parallel with other
slave say S5. And in theory, multiple masters can now can operate in parallel, as long as they are interacting with
unique different respective Slaves.

The AHB Multilayer solution can be leveraged from many companies.
Synopsys and ARM both offer their respective solutions.
While ARM Bus Matrix RTL code can be obtained for free (click here to get it) (as long as there is no commercial use).
Synopsys RTL code may not be available for free.

Synopsys offerings:
DW_ahb bus offered by Synopsys is a blocking (Normal Bus)
DW_ahb_icm bus offered by Synopsys is multi layered bus. However DW_ahb_icm is a single Slave bus,
so for building a MxS system where M is number of Masters and S is number of Slaves, 'S' counts of
DW_ahb_icm must be used, as shown in the diagram here.

The AHB Multilayered BUS typically acts on AHB Lite. The HBUSREQ, HGRANT are not required. Any master
can start a transaction in any clock cycle, without worrying about first requesting the bus-access. If the slave it intends
to transfer is busy, the address/control phase is captured by the Multilayered Bus, and the HREADY towards the
master is pulled Low, till the busy slave gets un-busy, and then the transfer resumes.
Hence typically the AHB multilayered Bus designs wont have HBUSREQ/HGRANT signals. However there is no reason why
these design cannot support other AHB features which are not part of AHB Lite, for example Split/Retry response.
The elimination of HBUSREQ/HGRANT has an added advantage, that it saves a clock cycle.

One other thing to consider is the following:
Most of ARM Cortex-M processors's AHB interface are always AHB-Lite. So these does not have any HBUSREQ/HGRANT
signals. So these cannot be connected to a traditional normal, single layered AHB bus directly.

ARM AHB Bus Matrix Vs Synopsys Multilayer Bus

ARM's Solution	Synopsys' Solution
Very Small in terms of Area. Hence very efficient in terms of Area/Power	Since it is built using multiple DW_ahb_icm IPs. its quite large as compared to ARM's Bus Matrix.
Takes 1 clock cycle extra, when master start a new transaction after being Idle, or when master Switches Slave.	No extra clock cycle. The Control phase of AHB appears at the slave in the same clock. Just combo delay.
Can achieve higher Maximum frequency of operation, since the timing path is broken. (and hence 1 clock cycle delay)	Wont be able to achieve as higher frequency of operation as the ARM Bus Matrix.
RTL can be obtained for free as long as no commercial use. Great for learning, Great for students.	No Freebies here.