|Has 1 address channel, 1 read
data channel, 1 write data
||Has 1 read address channel, 1
write address channel, 1 read data channel, 1 write data
channel. 1 write response channel That is altogether it has
5 parallel channels. (The first AXI version had just 1
|Does not support outstanding
reads, though with writes, the master can issue multiple
write transactions, marking them as 'bufferable' so that if
the interconnect is able to respond immediately, the master
would consider the transaction over, and would issue
subsequent transactions immediately in the next clock cycle.
||Has native support for multiple
|No concept of channels.
||AXI supports transaction IDs. The
user may issue multiple outstanding transactions per
transaction ID. A transaction ID can relate to a data
stream. Hence by issuing multiple outstanding transactions
per ID, AXI gives the user the power to have 'channels' of
|It does not support pipeline
registers in its path, if user is not able to meet timing
||User can insert a pipeline
register anywhere in the path of any of the 5 channels,
which helps in timing closure and help achieve higher
|Due to its in-ability to support
pipeline registers insertion, AHB limits the max freq for
the design. This can hit hard, on the SoCs which are big,
and may have long distances for the datapath to cover.
||AXI enables higher frequency of
operation due to its support for 'pipe-line' register
|Number of wires are less
||Since AXI has 5 parallel channels
running, it has a lot of more wires, which may cause
congestion in layout.
||Extremely high Throughput
|No inherent support for side-band
||AXI 4 supports AxUSER bits, i.e.
it has support for side-band signals.
|No QoS Support
||AXI 4 supports QoS
|Burst Lengths are fixed i.e 1, 2,
6, 16 except for INCR types, where it can be anything as
long as it does not cross 4K boundary.
||Burst lengths can be anything,
from 1-16 for AXI3, and 1-256 for AXI4.
|The 'INCR' type burst can have
any length, but there is no information available at the
start of the burst, how long it might be.
||The length of the burst is always
known right at the start. This feature is supported by using
|Strongly Ordered: Since there is
at a time only 1 active transactions, the transactions are
strongly ordered in the sense, that the responses received
to any transaction(s) follow the same sequence as the
transactions were issued.
||Since it supports multiple
outstanding transactions, i.e. many transaction is issued at
a time, the responses to different transactions can arrive
out of order. However the responses to each 'channel' will
still be ordered, i.e to say responses with same ID must
return in order
|Low power dissipation
||Higher power dissipation.
|Write Strobes are not supported.
||Write Strobes Are supported
|Locked Transfers are supported
||AXI3 supports Locked Transfers,
AXI4 does not support Locked Transfers.
|Exclusive transfers are Not Supported
||Exclusive transfers are supported.
It is to be noted again, that if there are no clock delays between a
master and a slave, and if we assume only 1 master and 1 slave in
the system, then again the AXI performance will be equal to AHB
performance, if we are doing only reads or only writes.