Cortex M4 Power management methodology supports 2 sleep modes
2. Deep Sleep.
From M4F processor logic point of view, there is little difference between the above two sleep modes. However, it’s the way these sleep modes may be utilized and/or implemented, which may make a difference. For example, the first i.e. the ‘Sleep’ mode may be implemented such that it’s only the clocks to the processor and any related logic which are stopped and the ‘Deep Sleep’ may be implemented such that the clocks and power both can be switched off to the processor. Its to be noted that if a WIC is implemented, the corresponding functionality is not available in ‘Sleep’ mode for M4F processor. i.e. the WIC’s functionality and features are only available in ‘Deep-Sleep mode’ for M4F processor. Deep Sleep in turn can be implemented with and without state retention.
The M4F processor has a register called SCR ‘Status control Register’. This register has a bit which selects between the ‘Sleep’/’DeepSleep’ modes. The subsystem software will write to this bit to indicate which sleep mode is required, when the processor next enters the sleep mode. The processor enters the sleep mode by executing an instruction called ‘WFE (wait for event) or WFI (wait for Interrupt)’. Soon after the processor has executed one of these instructions, the processor will assert a hardware signal (o/p signal w.r.t the processor itself) to let the outside world know that its OK to stop clock and/or power to the processor.
The M4F processor may be implemented using what is called the SRPG methodology. SRPG stands for State Retention Power Gating. This allows the internal ‘state’ of the processor to be ‘retained’ during low power modes, such that when the power is re-applied to the processor, it starts working from where it was before entering the sleep mode. This is an alternative method which may be used as opposed to copying the ‘state’ of the processor in RAMs, and then re-copying the state from RAM to back to the processor on power up. Of course, this is very helpful in reducing the turn-on time for a processor from deep-sleep state, however since it is implemented using ‘state retention’ flops, it will consume power while in deep-sleep state. Usually, all the sequential elements inside the processor are ‘retained’, and these state retention flops are powered by a different power rail. The implementation SRPG will require specific control over how the reset is applied, as while coming out from the deep-sleep mode which uses state-retention, the processor reset cannot be applied.
The use of this methodology is also technology dependent, as the technology library must support ‘retention’ flops or something equivalent.
The WIC or Wake-up Interrupt Controller is an optional component with the M4F processor. The WIC is used to help wake-up of the processor from deep-sleep power state, when a valid interrupt is received at its boundary. While going into the deep-sleep mode, some of the data e.g. interrupt makes & priorities are copied from the processor NVIC to the WIC automatically. There are also a couple of hand-shake signals which must be activated, to agree that the next deep-sleep mode the processor will enter, will be a WIC enabled one.
WIC is a configuration option and can be used/omitted as required.
WIC has no program-able registers. It has nothing to do with software, it is completely transparent to software.
In principle the WIC can be implemented without a clock as well, where it requests to the power controller to make its clock/power available, as a valid interrupt is asserted towards it. However, this is not usually done, as it requires change to the generated RTL, and the implementation has some limitations and after-effects which must be taken care of.
Based upon the capabilities and the option(s) available for the M4F processor, following is the summary of what power management modes may be implemented
1. Light Sleep Mode: Where only clock(s) i.e. FCLK and HCLK to the processor are stopped.
2. Deep Sleep Mode: Where the power domain containing the M4F processor may be switched off. This mode can be further categorized into two kinds
a. Deep Sleep with State Retention: It will allow fast wake-up times at an expense of increased leakage. Following a wake-up the processor is in a state which is the same as the state it was in before going into Deep Sleep.
b. Deep Sleep without State retention: It will allow most power savings at an expense of decreased wake-up times. Before going to Deep Sleep, the processor state will have to be stored in SRAMs. Following wake-up, the processor will have to be re-initialized from scratch, before it will come in a state in which it was before going into deep-Sleep.