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--Generated by Utility gen_entity.pl by Aviral Mittal
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--Copy Right Aviral Mittal avimit@yahoo.com
--Any Reproduction of this code in part or whole is 
--is strictly prohibited without the written consent of
--The copy right holder
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LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE std.textio.ALL;
USE IEEE.std_logic_textio.ALL;

ENTITY tb IS
        GENERIC(wi : integer := 2);
END ENTITY;

ARCHITECTURE behav OF tb IS
--Signal Declaration Section
 SIGNAL Clk : std_logic := '0';
 SIGNAL rst_n : std_logic := '0';
 SIGNAL count_enable : std_logic := '0';
 SIGNAL count_out : std_logic_vector(wi downto 0);
--Signal Declaration Section Ends

COMPONENT counter

PORT (
 Clk : IN std_logic;
 rst_n : IN std_logic;
 count_enable : IN std_logic;
 count_out : OUT std_logic_vector(wi downto 0)
);
END COMPONENT; -- counter

BEGIN
counter_I0:counter
 PORT MAP (
 Clk => Clk,
 rst_n => rst_n,
 count_enable => count_enable,
 count_out => count_out
);

  Clk <= not(Clk) after 5 ns;

  rst_n <= '1' after 21 ns;

  count_enable <= '1' after 41 ns,
               '0' after 72 ns,
               '1' after 101 ns;
END behav;