--##############################################################################
--                               Copyright
--##############################################################################
--
--     Copyright Aviral Mittal (C) 2003 
--
--     All rights reserved. Reproduction in whole or part is prohibited
--     without the written permission of the copyright owner.
--
--##############################################################################
--  Entity Name       :  counter
--##############################################################################

LIBRARY ieee;
    use ieee.std_logic_1164.ALL;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

ENTITY counter IS
  GENERIC(wi : integer := 2);
  PORT 
    (
    Clk : IN std_logic;
    rst_n : IN std_logic;
    count_enable : IN std_logic;
    count_out : OUT std_logic_vector(wi downto 0)
    );

END counter;


--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------

ARCHITECTURE rtl OF counter IS

SIGNAL count_out_sig : std_logic_vector(wi downto 0);

BEGIN
  count_reg: PROCESS(clk)
  BEGIN
    IF(rising_edge(clk)) THEN
      IF(rst_n = '0') THEN
        count_out_sig <= (others => '0'); --Sync reset
      ELSIF(count_enable = '1') then 
        count_out_sig <= count_out_sig + 1; 
        --increment 'dat_out_sig' if 'count_enable' = '1' ONLY.
      ELSE
        count_out_sig <= count_out_sig; 
        --The above line is not required, but is written for clearity
      END IF;
    END IF;
END PROCESS count_reg;

count_out <= count_out_sig;

END rtl;