--##############################################################################
--                               Copyright
--##############################################################################
--
--     Copyright Aviral Mittal (C) 2003 
--
--     All rights reserved. Reproduction in whole or part is prohibited
--     without the written permission of the copyright owner.
--
--##############################################################################
--  Entity Name       :  counter
--##############################################################################

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY counter IS
        GENERIC(wi : integer := 15);

	PORT (
		clk : IN std_logic;
		reset : IN std_logic;
		enable : IN std_logic;
		dat_out : OUT std_logic_vector(wi downto 0)
	);

END counter;


--------------------------------------------------------------------------------
--
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ARCHITECTURE rtl OF counter IS

FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
                  --this function increments a std_logic_vector type by '1' 
        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
        BEGIN 
        tb(s1'low) := en; 
        V := s1; 
        for i in (V'low + 1) to V'high loop 
            tb(i) := V(i - 1) and tb(i -1); 
        end loop; 
        for i in V'low to V'high loop 
            if(tb(i) = '1') then 
                V(i) := not(V(i)); 
            end if; 
        end loop; 
        return V; 
        end incr_vec; -- end function 

FUNCTION  dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
                  --this function decrements a std_logic_vector type by '1' 
        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
        BEGIN 
        tb(s1'low) := not(en); 
        V := s1; 
        for i in (V'low + 1) to V'high loop 
            tb(i) := V(i - 1) or tb(i -1); 
        end loop; 
        for i in V'low to V'high loop 
            if(tb(i) = '0') then 
                V(i) := not(V(i)); 
            end if; 
        end loop; 
        return V; 
        end dcr_vec; -- end function 



SIGNAL dat_out_sig : std_logic_vector(wi downto 0);

BEGIN

	count_reg: PROCESS(clk)
	BEGIN
        IF(rising_edge(clk)) THEN
	  IF(reset = '0') THEN
            dat_out_sig <= (others => '0'); --Sync reset
          ELSE
            dat_out_sig <= incr_vec(dat_out_sig,enable); 
            --increment 'dat_out_sig' if 'enable' = '1' ONLY.
          END IF;
        END IF;
	END PROCESS count_reg;

dat_out <= dat_out_sig;

END rtl;