remove_design -all
set search_path {/homes/amittal/s5/work/physical_lib/corelib/tsmc_090_g_art}
set target_library {scadv_tsmc_cln90g_lvt_ss_0p9v_125c.db}
lappend search_path {[exec pwd]}
lappend search_path {.}
set link_library  {PLL10CCMID_W_125_1.35.db}
read_vhdl counter_top.vhd 
read_vhdl counter.vhd
create_clock -period 10 -name design_clk clk
set_input_delay 4.0 [remove_from_collection [all_inputs ] clk] -clock design_clk
set_output_delay 7.0 [all_outputs] -clock design_clk
set_max_area 0
set_clock_gating_style -minimum_bitwidth 2
set_svf -append "counter_top.svf"
set compile_seqmap_propagate_constants true
set compile_delete_unloaded_sequential_cells false
set hdlin_ff_always_sync_set_reset "true"
current_design counter_top
compile -map_effort high
write -format ddc -output counter_top.ddc -hier
write -format ddc -output counter_top.vlog -hier
ungroup -all -flatten
write -format verilog -output counter_top_flat.vlog
quit