LIBRARY ieee;
USE ieee.std_logic_1164.all;

--TEMPLATE TESTBENCH

ENTITY counter_top IS
        GENERIC(wi : integer := 15);

        PORT (
                clk : IN std_logic;
                reset : IN std_logic;
                sel_count : IN std_logic;
                enable : IN std_logic;
                dat_in : IN std_logic_vector(wi downto 0);
                dat_out : OUT std_logic_vector(wi downto 0)
        );
END counter_top; 

ARCHITECTURE HIER of counter_top IS

SIGNAL dat_out_sig	:	std_logic_vector(wi DOWNTO 0);
COMPONENT counter
PORT (
clk	:	 IN std_logic ;
reset	:	 IN std_logic ;
enable	:	 IN std_logic ;
dat_out	:	 OUT std_logic_vector(wi DOWNTO 0)
);
END COMPONENT;
 
BEGIN

counter_i0: counter
PORT MAP (
clk => clk,
reset => reset,
enable => enable,
dat_out => dat_out_sig
);

process(sel_count,dat_in,dat_out_sig)
begin
  if(sel_count = '1') then
    dat_out <= dat_out_sig;
  else
    dat_out <= dat_in;
  end if;
end process ;

END HIER;