Formality Commands Used On Live Project(s)
set_constant -type cell {r:/WORK/a926ejsIBIU/CurrentAddr_reg[1]} 0

guide
guide_reg_constant -design ARM926EJS_WRAP U1/uCORE/u9EJ/uARM9/uCORECTL/uIPIPE/uJDEC/NxtStateD_reg[7] 0
setup

The above commands sets the reference design register to a constant. Note no 'r:' has been mentioned

read_verilog -container r -libname WORK /homes/amittal/s5/hw/rtl/unit/arm/src/ARM926EJS_WRAP.v
set_top r:/WORK/ARM926EJS_WRAP
read_verilog -libname WORK -netlist -c i /homes/amittal/s5/hw/rtl/unit/arm/AT230-BU-00000-r0p5-01rel1/synopsys/build_dir/ARM926EJS_WRAP.v
set_top i:/WORK/ARM926EJS_WRAP
verify
report_black_box
report_passing
report_failing
report_matching


set verification_clock_gate_hold_mode low  : used in RTL vs Netlist for specifing  clock  gating.
set hdlin_enable_rtlc_vhdl true
set_constant  i:/WORK/ARM926EJS_WRAP/ScanEnable 0 -type port
set_constant  r:/WORK/ARM926EJS_WRAP/ScanEnable 0 -type port
set_dont_verify_point i:/*/ARM926EJS_WRAP/*ScanOut[*]
set_dont_verify_point r:/*/ARM926EJS_WRAP/*ScanOut[*]
set_reference_design  r:/WORK/ARM926EJSCore
set_implementation_design  i:/WORK/ARM926EJSCore
set_black_box i:/WORK/ARM_RAM_WRAPPER
set_black_box r:/WORK/ARM_RAM_WRAPPER

remove_black_box i:/WORK/ARM_RAM_WRAPPER
remove_black_box r:/WORK/ARM_RAM_WRAPPER

BACK[How to Run Formality]                              NEXT[Run Log and a brief Explanation ]

HOME