Formality Introduction:

Formality is a tool from Synopsys, which is used for Formal Verification.
Formal verification is a method to verify two designs without running
simulations that they are functionally equivalent. Of course one design
is the 'reference' design, which is supposed to be a 'good' design, and
the second design which is called implementation design, is what is
sought to match the 'reference' design.

Usually two kinds of verification are common using formality
I would use ref for reference and impl for implementation hence forth.
1. RTL(ref) vs Netlist(impl)
2. Netlist vs Netlist

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