Formality is a
tool from Synopsys, which is used for Formal
verification is a method to verify two designs without running
simulations that they are functionally
equivalent. Of course one design
is the 'reference'
design, which is supposed to be a 'good'
the second design which is called
implementation design, is what is
match the 'reference' design.
kinds of verification are common using formality
I would use
ref for reference and impl for implementation hence forth.
1. RTL(ref) vs
2. Netlist vs
NEXT( Why Use