Low Power design Techniques for digital systems:

The following techniques are applicable at RTL level, or architectural level,
which may help reduce power consumption. The focus here is to reduce the switching
activity in a digital system. Switching power is the only thing which might be reduced
once the process, technology and voltage is decided for a system/block to reduce power

1). Clock Gating : Shut off the clock to a block not currently in use.

2). Pipelining : Increases throughput, reduces frequency of operation.

3). Grey Coding : Hamming distance of 1, reduces transitions, i.e switching activity. Use them for
address bus or counters or state codes for state machines.

4). Bus Invert Coding : Invert bus if hamming distance is grater than 1/2 word size.

5). Power Supply Shut Down : Power supply to a block may also be shut down to a block
when not in use.

6). Distributed Memory : Use different clocks to different memories as per requirement,
 slow clocks will reduce power consumption. Having a shared memory system may un-necessarily
increase the rate of switching activity.

7). Sign Magnitude instead of Two's compliment : Two's compliment representation
makes more transitions in word than sign-magnitude representation, when there is a sign
change. Hence using sign-magnitude representation reduces power consumption.

8). Avoid Glitches : Glitches are again unwanted transitions, try to avoid them, again using grey
codes for address/counters in your design, the glitches may be avioded.

9). Asynchronous Design Techniques : Asynchronous design reduces switching activity a lot, and
hence helps in reduction of power. But there are potential risks associated with asynchronous design.
Also EDA tools don't like them. Testability is another issue with these designs.

Author : Aviral Mittal