#!/usr/bin/perl
##//////////////////////////////////////////////////////////////////////////////
##                        Coypright (C) Aviral Mittal.
##//////////////////////////////////////////////////////////////////////////////
##   All rights reserved. Reproducion in whole or in part is prohibited without
##   written consent of copyright Owner.The professional use of this material
##   is subject to the copy right owners approval in written.
##//////////////////////////////////////////////////////////////////////////////
################################################################################
# This script converts a VERILOG Module into Empty VHDL Entity
# IMP : The verilog input file should be clean(i.e with no syntax errors)
#       Since this script assumes that the input file has no syntax errors,
#       Funny results can be seen if the input file does have syntax errors. 
# Usage:
# 
# unix > ./vl2vh.pl <verilog file> 
#
################################################################################
if(@ARGV[0] eq "") {
  print "ERROR: Insufficient input fields\n";
  print "\n";
  print "Usage:unix> ./vl2vh.pl <verilog file> \n";
  print "\n";
  exit;
}
################################################################################
# Initialization of certain pre-defined variables
################################################################################
system ("perl -i.bak -p -e 's#;#;\n#ig' @ARGV[0]");
$i = 1;
$j = 1;
$module_found = 0;
open(out,">@ARGV[0].vhdl") || die "Couldn't open output file.\n ";
#open(out1,">vvlog") || die "Couldn't open output file.\n ";

print "-----------------\n";
print "output file is $ARGV[0].vhdl\n";
print "-----------------\n";

################################################################################
# Parser Begins Here
################################################################################
open(infile0,"<@ARGV[0]") || die "Couldn't open infile0. @ARGV[0]\n ";
    while ($line = <infile0>) {
    if($line =~ /module/) { #try to find the keyword module, if not find,
                            #dont start anything
      $module_found = 1;
    }
  if( $module_found == 1) {
    chomp($line);
    @lines = split(/\/\//, $line); #Split the line using verilog comment
                                   #the first part is useful, the second part
                                   #is discarded
    #print out1 "comented line = $line\n";
    #print out1 "uncommented line = $lines[0]\n";
    
      $lines[0] =~ s/^(\s+)//;
      $myline = $myline.$lines[0];
      if($myline =~ /;/) {
        $compline = $myline;
        $myline = "";
        print "compline = $compline\n";
      }
      else {
        $compline = "";
      }
      if($compline =~ /^(input|output|inout)\s+(\[(\d+):(\d+)\])\s+(.*)/ ) {
      #if($line =~ /^(input|output|inout)\s+(\[(\d+):(\d+)\])\s+(.*)/ )
        print "found 1=$1 1=$2 1=$3 1=$4 1=$5\n";
        #found input [13:0] 13 0 testDAC;
        if($1 eq 'input') {
          $direction = 'IN';
        }
        elsif($1 eq 'output') {
          $direction = 'OUT';
        }
        elsif($1 eq 'inout') {
          $direction = 'INOUT';
        }
        @port_names = split(/\,/, $5);
        foreach $port_name(@port_names) {
          #$port_name = $5;
          $port_name =~ tr/;/ /;
          print out "    $port_name : $direction std_logic_vector";
          if($3 >= $4) {
            print out "\($3 downto $4\);\n";
          }
          else
          {
            print out "\($3 to $4\);\n";
          }
        }#foreach
      }#if($compline =~ /(^input)\s+(\[(\d+):(\d+)\])\s+(.*)/ )



      elsif($compline =~ 
           /^(input|output|inout)\s+(\[(\d+)(\s+[:]\s+)(\d+)\])\s+(.*)/ ) {
        print "found 1=$1 1=$2 1=$3 1=$4 1=$5 1=$6\n";
        #found input [13:0] 13 0 testDAC;
        if($1 eq 'input') {
          $direction = 'IN';
        }
        elsif($1 eq 'output') {
          $direction = 'OUT';
        }
        elsif($1 eq 'inout') {
          $direction = 'INOUT';
        }
        @port_names = split(/\,/, $6);
        #@port_names = split(/\,/, $5);
        foreach $port_name(@port_names) {
          #$port_name = $5;
          $port_name =~ tr/;/ /;
          print out "    $port_name : $direction std_logic_vector";
          if($3 >= $5) {
            print out "\($3 downto $5\);\n";
          }
          else
          {
            print out "\($3 to $5\);\n";
          }
        }#foreach
      }#if($compline =~ /(^input)\s+(\[(\d+):(\d+)\])\s+(.*)/ )
 

      elsif($compline =~/(^module)\s+(.*)/) {
        print "1= $1 2=$2\n";
        @module_name = split(/\(/, $2);
        print "module_name = @module_name[0]\n";
        print out "LIBRARY ieee;\nUSE ieee.STD_LOGIC_1164.ALL;\n";
        print out "ENTITY $module_name[0] IS\n";
        print out "  PORT \( \n";
      }#elsif($compline =~/(^module)\s+(.*)/)
      elsif($compline =~/^(input|output|inout)\s+(.*)/) {
        $direction = $1;
        print "mult in out or inout =$1: $2\n";
        @port_names = split(/\,/, $2);
        print "portnames = @port_names\n";
        if($direction eq 'input') {
          $direction = 'IN';
        }
        elsif($direction eq 'output') {
          $direction = 'OUT';
        }
        elsif($direction eq 'inout') {
          $direction = 'INOUT';
        }
        foreach $element(@port_names) {
          $element =~ s/ //;
          $element =~ s/;//;
          print out "    $element : $direction std_logic;\n";
        }
      }
  }#( $module_found == 1)
    } #while ($compline1 = <infile0>)
    print out "\);\n";
    print out "END $module_name[0];\n";
    print out "ARCHITECTURE empty of $module_name[0] IS\n";
    print out "BEGIN\n";
    print out "END empty;\n";
    close(out);
system ("mv -f $ARGV[0].bak $ARGV[0]");
print "-----------------\n";
print "output file is $ARGV[0].vhdl\n";
print "-----------------\n";
################################################################################