--Generated by genEntity.pl Report Problems to aviral.mittal@intel.com
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.fun_pkg.ALL;
library synopsys;
USE synopsys.attributes.ALL;

ENTITY binary_counter IS
  GENERIC ( wo : integer := 32);
  PORT (
    clk : in std_logic;
    rstn : in std_logic;
    count_en : in std_logic;
    count_out : out std_logic_vector(wo-1 downto 0)
  );
END binary_counter;

ARCHITECTURE rtl OF binary_counter IS
--SIGNAL Declaration Section Starts
  SIGNAL count_out_sig: std_logic_vector(wo-1 downto 0);
  SIGNAL rstn_sig : std_logic;
  attribute sync_set_reset of rstn_sig : signal is "true";
--SIGNAL Declaration Section Ends
  BEGIN
  rstn_sig <= rstn;
count_p : PROCESS(clk)
  BEGIN
  IF(rising_edge(clk)) then
    IF(rstn_sig = '0') THEN
      count_out_sig <= (others => '0');
    ELSE
      count_out_sig <= incr_vec(count_out_sig,count_en);
    END IF;
  END IF;
END process count_p;

count_out <= count_out_sig;

END rtl;