--Template testbench generated by genTemplateTb.pl for binary_counter
LIBRARY IEEE ;
   USE IEEE.std_logic_1164.ALL ;
   USE work.fun_pkg.ALL ;

ENTITY binary_counter_tb is 
 GENERIC 
( wo : integer := 32 ) ;  
END binary_counter_tb ;

ARCHITECTURE tb of binary_counter_tb is 

signal clk : std_logic  ;
signal rstn : std_logic  ;
signal count_en : std_logic  ;
signal count_out : std_logic_vector ( wo-1 downto 0 )    ;

--TB SIGNALS
signal tb_clk     : std_logic := '0' ;
signal tb_rstn    : std_logic := '0' ;
signal tb_counter : integer   := 0 ;
signal tb_counter_vec : std_logic_vector(31 downto 0) := (others => '0') ;

-- synopsys translate_off
constant tb_clk_period : time := 5 ns;
-- synopsys translate_on

component binary_counter
PORT ( 
  clk : in std_logic  ;
  rstn : in std_logic  ;
  count_en : in std_logic  ;
  count_out : out std_logic_vector ( wo-1 downto 0 )    
);
END COMPONENT ;

BEGIN
binary_counter_u1 : binary_counter
PORT MAP( 
  clk => tb_clk ,
  rstn => tb_rstn ,
  count_en => count_en ,
  count_out => count_out 
);

-- synopsys translate_off
tb_clk <= not(tb_clk) after tb_clk_period ;
tb_rstn <= '1' after tb_clk_period * 5 + 1 ns;
-- synopsys translate_on

tb_counter_p : PROCESS (tb_clk)
begin
if(tb_rstn = '0') then
  tb_counter <= 0;
elsif(rising_edge(tb_clk)) then
  tb_counter <= tb_counter + 1;
  tb_counter_vec <= incr_vec(tb_counter_vec,'1');
end if;
end process tb_counter_p;

count_en <= tb_counter_vec(7);

END TB;