System on Chip Architecture Fundamentals:
-Aviral Mittal (avimit att yhaoo datt camm)
Connect Aviral Mittal @ https://www.linkedin.com/in/avimit/


SITE HOME
Skip Theory Go Straight to SoC Design Web Training With ARM Cortex-M3


SoC Components:


1. I/O Pads:
For a SoC to be able to interact with the outside world, the least is needed are input/output pins.
Since these pins also called ports will carry information from inside the SoC to outside the SoC and vice-versa, these I/O ports are specially design circuits, which are called I/O pads. The electrical characteristics of off-chip metal is quite different to the electrical characteristics of on-chip metal, for example outside the SoC chip, these I/O pads have to drive very thick metal wires with very high capacitance, while inside the chip those wires are very thin.
So we need especially design I/O pads with special circuitry to deal with harsh outside world and relatively comfortable inside world.
A collection of these I/O pads for a chip is also often termed as I/O Pad Ring, as usually these pads are arranged in the form of a Ring around at the periphery of the chip surrounding the 'core' logic.
Each I/O pad can be either input pad, or an output pad or a bi-directional pad.
Then Each I/O pad can be either analog pad to carry analog signal or a digital pad to carry digital signal.
And then there are power pads such as VDD pad and GND (also called VSS) pad for supplying power to the chip.

ESD Protection:
One of the secondary purpose of the PADs is to protect the internal chip-circuit from over-voltage pulses. This may be due to electrostatic charges, or due to human error while accidentally a user has applied higher than specified voltage to a pin.

Voltage conversion:
Some pads may provide a voltage conversion facility. i.e. they may be able to translate voltage levels and sort out the difference between external and internal voltages.

What are pad drivers?
The output pads are required to drive relatively high amount of currents, as these will connect to off-chip metallic wires, which may connect to other circuits. For this purpose there are special purpose circuits designed to provide high current to the output pads. These are often called pad drivers.

What are GPIOs?
While some pads on the SoC has specific purpose, others can be general purpose. These general purpose pads are calld GPIOs. They do not have a defined function as such, but can be very useful to add functionality to the post-production device. These GPIOs can easily be made available to the SoC software which can then use it for a variety of purposes.

I/Os dedicated to DFT:
There is another function associated with the I/O pads. This is to help with the manufacturing test of the SoC. These pads usually do not participate in functionality of the SoC, but helps in the testing of the Chip. So the SoC has some core logic and I/O pads dedicated to what is called 'Design For Test' Logic or simply DFT logic. More about DFT is presented in later section(s).

I/Os dedicated to Debug & Trace:
A SoC will have software running on it. To be able to debug the software, the SoC provides extra logic which helps the software developers to debug their software.
Then their are SoC I/Os dedicated to this debug enablement. A very common standard is JTAG, another common standard is SWD (Serial Wire Debug). Note that both JTAG/SWD can also provide some DFT related functionality. A JTAG port on the SoC device will have 4-5 I/Os where as Serial Wire Debug port can reduce the number of SoC level I/Os to 2.


Pull-up/Pull down functionality associated with I/Os
The I/O pads are often connected to either Ground or VDD inside the SoC so that they can go to GND voltage or VDD voltage, when they are not connected to any logic outside the SoC. That means if an I/O is just kept unconnected or floating outside the SoC, it will attain either a GND voltage or VDD voltage depending upon if this I/O is internally connected to GND (via a resistance) or VDD (via a resistance).
Note that the resistance value will have to be very high, so that there is minimal current leakage. And also because these values must easily be overridden when driven by some other source. (i.e. when they are connected to something rather than left floating). Since they are easily overridden, and are connected using very high resistance, these are often called 'weak pull-up' (connected to VDD via resistance) or 'weak-pull down' (connected to Ground via resistance)

More theory is being uploaded.. pls keep on checking.
Stage 1 Practical is now ready to be used and downloaded Click on Next below:

Click Here to Make Comments or ask Questions

<= Previous                                                                                                                Next =>