System on Chip Architecture Tutorial
-Aviral Mittal

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Which ARM Cortex-M processor?
Perhaps the most important aspect of any SoC design will be to select the main application processor on the SoC. This application processor will typically run an operating system, though for very small applications, the OS may not be needed.
As indicated earlier, the scope of this techerature limits the processor type to ARM Cortex-M, so the processor selection will be one of the ARM Cortex-M. Here is a very brief selection criteria:

ARM Cortex-M0
M0 is the smallest processor with about 12K Gates in min configuration: Suitable for very low power applications, with low performance requirements. It will be sufficient for Blue-Tooth Processing. However it does not have security features, and it does not have support for trace components e.g ITM (Instrumentation Trace Macrocell) or ETM (Embedded Trace Macrocell) or MTB (Micro Trace Buffer). Dont worry about what these ITMs and ETMs and MTBs are, all you need to understand is, without ITM and/or ETM and/or MTBs, debugging your application software code will become a bit difficult. But then M0 code are typically simpler and small, so one would argue the need for these components at the first place.
Bus protocol: AHB-Lite
Gate Count: 12 K in Min Config, this is the ARM quoted figure.
ARM Cortex M0 Gate Count (Nand 2 equivalent gates): ~25 K Gates. This is what I obtained from synthesis by dividing reported area by design compiler by the area of 1 Nand 2 gate area of minimum strength from the tech lib.

Note: This techerature will always use the Nand 2 equivalent gate count as the metric for area analysis and area comparison. It is clear that the Gate Count Quoted by ARM is not equivalent Nand 2 gates, but it is total number of gates. And it is to be noted that ARM quoted 12K Gate figure for M0 may be misleading if you are after actual Nand 2 gate count, which is a better metric.

ARM Cortex-M0+
M0+ provides support for hardware security. It offers a privileged and un-privileged mode of operation distinction with optional Memory Protection Unit. (MPU). It also provides optional MTB (Micro Trace Buffer) for enhanced debug capabilities. So if you are worried about basic security and about debugging your code, yet want a very energy efficient small processor, Cortex - M0+ is perhaps the right choice for you.
Bus Protocol: AHB-Lite
Gate Count: Not Known

ARM Cortex-M3
ARM Cortex-M3 packs a bit of more processing power as compared to Cortex-M0 or M0+. It adds MAC (multiply accumulate) instruction by default to support single cycle Multiply, which is optional in M0, M0+, increases interrupts from 32 to 240, adds hardware divide unit, upgrades to ARMv7-M instruction set architecture, and has ETM (Embedded Trace Macrocell) support for enhanced trace & debug capabilities.
Obviously it retains the privileged and un-privileged mode of operation distinction with optional Memory Protection Unit. (MPU).
Bus Protocol: AHB-Lite + APB
ARM Cortex M3 Gate Count (Nand 2 equivalent gates): ~105 K Gates.
So the price for choosing Cortex-M3 over M0, is about 4-4.5 times in terms of Area.

ARM Cortex-M4
ARM Cortex-M4 packs even more processing power as compared to M3. It adds 'SMID' (single instruction multiple data) instructions, and completes some instructions in single clock cycle as compared to multi clock cycle execution in M3. Its suitable for adding DSP applications to your SoC. It offers a single precision Floating Point Unit as an option. So if you want to run some DSP applications, then this is the processor for you.
Bus Protocol: AHB-Lite + APB
ARM Cortex M4 Gate Count (Nand 2 equivalent gates): ~180 K Gates with FPU.
So the price for choosing Cortex-M4 over M3, i.e. the price for adding DSP applications, is about ~2 times in terms of Area.

ARM Cortex-M33
ARM Cortex-M33 is primarily for added hardware security. It adds ARM TrustZone Support, interrupt lines increases to 480, it adds a optional co-processor interface, and has the optional FPU + DSP instructions. So this is more like an Cortex-M4 with added security. Not sure why its called M33, I would rather call it M44.
So if the privileged and un-privileged mode falls short for your security requirements, and you must have ARM TrustZone, then this is the processor for you. Note that the protocol is now AHB5 (unlike AHB-Lite).
Bus Protocol: AHB5 + APB
ARM Cortex M33 Gate Count (Nand 2 equivalent gates): Not Known, but I will say it should be very similar to Cortex-M4, so let me estimate it to ~200 K Gates with FPU.

ARM Cortex-M7
ARM Cortex-M7 is primarily for system requiring more performance. It has dedicated Tightly Coupled Memory interfaces, the instruction TCM (ITCM) and the Data TCM (DTCM), where you can place your critical code, which will run very fast. It also has AXI interface, which can again boost up the performance. You also get Built in Optional Instruction-Cache and Data-Cache which can again boost up the performance.
However from security point of view it does not support ARM TrustZone.
Bus Protocol: AXI + AHB-Lite + APB.
ARM Cortex - M7 Gate count: Not known.

ARM Cortex -M7+
This processor is my guess work. I think this will be adding trustzone to Cortex-M7.

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