OVM/UVM Tutorial Using System Verilog

-Aviral Mittal


M(B)illion Dollar Question:
Why? why OVM/UVM

One may argue, what is the need of OVM/UVM? why OVM/UVM Exists?
Traditionally, test benches were written using VHDL or Verilog. The concept was simple, drive inputs to DUT,
Observe Outputs, check if Outputs are as expected. However, this model could not keep pace with the

growing complexity of systems and growing complexity of SoC integration.

1.       The key question is: How and when would an engineer may declare that verification is complete?

2.       The other problem is Re-use? How do we re-use testbenches?

3.       And last and certainly not the least BUGS? Is your Verification Env good enough to catch bugs?


Tutorial Organization:
The tutorial starts with concise theory, followed by some practicals. If you are smart enough with the
theory part, keep on clicking 'Next' at bottom, till you see practicals.


Introduction:

OVM/UVM is a systematic and standardized way to write Test Bench or Test Environments for IPs, Subsystems etc.
The VLSI Industry has 2 principal languages to write advanced test benches and test environments.
One is Specman ‘e’ and the other is SystemVerilog.
Though Specman ‘e’ was the first language invented specifically for verification,
SystemVerilog arrived late, and it did take concepts from Specman ‘e’.

To be able to understand OVM/UVM concepts, its important to understand the following

1.       Concept of Constrained Random verification

2.       Concept of Interfaces

3.       Concept of Transaction level Modelling (TLM)



This site is under construction: Pls be patient...


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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.