Having understood the term 'constrained Random'
let us now focus on what are called Interfaces.
The interface is a system verilog term which
represents a set of signals collectively.
Usually these collection of signals are a form of some standard and are present on a DUT.
Since the DUT uses these collection of signals to interact with the rest of the world, it is called 'interface'.
For example, in the ARM world, an AHB interface is a very common interface found on various IPs,
sub-systems or modules.
A UVM test environment would usually 'drive' an Interface. For example let us take an AHB interface.
The following presents an AHB-type interface written using System-Verilog.
logic [32-1:0] haddr;
logic [1:0] htrans;
logic [2:0] hsize;
logic [2:0] hburst;
logic [3:0] hprot;
logic [32-1:0] hwdata;
logic [32-1:0] hrdata;
logic [1:0] hresp;