OVM/UVM: A Practical Tutorial Using System Verilog
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-Aviral Mittal

Concept of Interfaces:

Having understood the term 'constrained Random' let us now focus on what are called Interfaces.

The interface is a system verilog term which represents a set of signals collectively.
Usually these collection of signals are a form of some standard and are present on a DUT.
Since the DUT uses these collection of signals to interact with the rest of the world, it is called 'interface'.
For example, in the ARM world, an AHB interface is a very common interface found on various IPs,
sub-systems or modules.
A UVM test environment would usually 'drive' an Interface. For example let us take an AHB interface.
The following presents an AHB-type interface written using System-Verilog.

interface ahb_if();
  logic hclk;
  logic hresetn;
  logic [32-1:0] haddr;
  logic [1:0] htrans;
  logic hwrite;
  logic [2:0] hsize;
  logic [2:0] hburst;
  logic [3:0] hprot;
  logic [32-1:0] hwdata;
  logic [32-1:0] hrdata;
  logic hready;
  logic [1:0] hresp;
endinterface: ahb_if

Its AHB-type interface, not may be a full AHB interface, as it does not have all the AHB signals on it.
Its just used as an example to illustrate the concept of 'interface'.

Interfaces are used in UVM world, as a means of information exchange between the test env and the DUT.
The test environment or the UVM test-bench can either read or write to the signals on 'interfaces'.
These interfaces are then instantiated in a verilog module, and in the same module these interfaces
are connected to the DUT. We will see a practical code example with all of the above bit later in this tutorial.


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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.