Synthesizeable Verilog RTL modules:
-Aviral Mittal
(avimit att yhaoo dat cam)
Connect @ https://www.linkedin.com/in/avimit/
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Building Block Verilog Lego :) Modules:
BB_FIFO.sv : Synchronous Fifo Code in SystemVerilog RTL
BB_BIN2GRAY.sv : Convert Binary Value to Gray Code in Verilog RTL
BB_GRAY2BIN.sv : Convert Gray Code Value to Binary in Verilog RTL
BB_DECODE.sv : Simple Binary Decoder Verilog RTL
BB_ENCODE.sv : Simple Binary Encoder Verilog RTL
BB_FLOPARRAY.sv : Simple Flop Array Verilog RTL
BB_MEMARRAY1R1W.sv : Simple memory model Verilog 1 rd port 1 wr port, loading/dumping of memarray from/to txt file supported
BB_FINDFIRST.sv : Find location of First 0 or 1 in input Vec
BB_FIFO_ASYNC.sv : Silicon Worthy Verilog ASYNC FIFO (no comercial use permitted)
BB_FIFO_RR_ARB.sv : Generic Round Robin Arbiter