Synthesizeable Verilog RTL modules:
-Aviral Mittal (avimit att yhaoo dat cam)

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Building Block Verilog Lego :) Modules: : Synchronous Fifo Code in SystemVerilog RTL : Convert Binary Value to Gray Code in Verilog RTL : Convert Gray Code Value to Binary in Verilog RTL : Simple Binary Decoder Verilog RTL : Simple Binary Encoder Verilog RTL : Simple Flop Array Verilog RTL : Simple memory model Verilog 1 rd port 1 wr port, loading/dumping of memarray from/to txt file supported : Find location of First 0 or 1 in input Vec : Silicon Worthy Verilog ASYNC FIFO (no comercial use permitted) : Generic Round Robin Arbiter