////////////////////////////////////////////////////////////////////////////////
//Author Aviral Mittal
//ISLI 2005/2006
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
//module name = rx_tb
module rx_tb; 
//parameters Declaration Section
  parameter delaynumber = 17; //to count 18 clock cycles, 1 bit/per 18 clocks
  parameter totalbytes = 15; //15 total no of bytes/word to be tranfered 
  parameter bits_in_one_word = 10; //11 bits/word to be xfered including parity
  parameter timeoutcount = 50;
  
  parameter xdelay = 0;  // Set this parameter to set the delay of transmission
                          // lines to the the number of clocks, 
                          // the transmission line is expected to take.
                          // Set it to 0, for no delay transmission line.
  
  //The delay register is 18 bits wide only. So the range of xdelay is
  //from 0 to 17. THE TESTBHECN WILL NOT WORK IF xdelay IS NOT SPECIFIED
  //IN THE RANGE OF 0 to 17.

  //reset, stop bit
//parameters Declaration Section Ends
// Regs declaration Section
  reg clk; //master clock with a 30uS time period
  reg [4:0] delaycounter; //count 0->17, then again 0->17 and so on
  reg [4:0] bitcounter; //count 0->8, then again 0->8 and so on
  reg [4:0] xbytecounter;//to count no of word to be transmitted
  reg [bits_in_one_word:0] op_reg; //output reg 9 bits including parity
  reg reset; //a reset like signal, nothing happens until reset goes to '1'
  //In this test bench once reset goes to '1', it remains '1'.
  reg mystart;
  reg mystop;
  reg [bits_in_one_word-3:0] timeout_counter;
  reg [2:0] ps; //State Machine Present State
  reg [2:0] ns; //State Machine Next State

  reg [bits_in_one_word-3:0] prob; //To corrupt parity bit this 
                                   //register will be given random
                                   //values on each clock
  reg success_mod; //modified success to facilitate display of data on
                   //console Not used in design

  reg [delaynumber:0] delay_reg; //output reg 9 bits including parity


// Regs declaration Section Ends
//Wire declaration Section
  wire [7:0] data_out; //
  wire [5:0] fast_clk;
  wire success; //  
  wire load_op_reg; //Load the output register, when this is '1'
  wire shift_op_reg; //Shift the output register,when this is '1'
  wire parity; //Final Parity.
  wire timeout;//when '1' indicates that success did not arrive
  wire parity_int; //intermediate parity bit
  wire parity_int1; //intermediate parity bit
  wire parity_corr; //corrupts the parity bit
//Wire declaration Section Ends

//Integer declaration Section
  integer ii; //loop variable
//Memory array declaration
  reg[bits_in_one_word-3:0] mem [0:totalbytes]; //memory array. At the reset of simulation this 
  //array will be populated with values read from a text file called mem.txt


//Instantiation of Device Under Test (dut0) i.e the receiver.
 rx rx_dut0 (.data_out(data_out), .success(success), .rx_in(rx_in), .clk(clk)); 
 //rx rx_dut0 (.data_out(data_out), .success(success), .rx_in(rx_in), .clk(clk),.fast_clk(fast_clk)); 

// Following initial reads a file called 'mem.dat' and initialize 
// the 'mem' array with the values needed to be transmitted to the receiver
// by the testbench
initial
begin
  $readmemb("mem.dat", mem, 0, totalbytes);  //read from addres 0 to 15
  for (ii= 0; ii<totalbytes+1; ii=ii+1) $display("mem[%0d] %d", ii, mem[ii]);
  //$monitor ("time= %0d,op_reg=%d, rx_in=%b,delaycounter=%d",
  //$time,op_reg,rx_in,delaycounter);
end


initial
begin
  clk = 1'b1;
  reset = 1'b0;
  mystart = 1'b0;
  mystop = 1'b1;
  delaycounter = 5'b00000;
  bitcounter = 0;
  timeout_counter = 0;
  prob = 0;
  op_reg = 11'b00000000001;
  delay_reg = 18'b1111_1111_1111_1111_11; //to model the delay of the 
  //rx_in = 1'b0;
                                          //transmission line
  #1000001 reset = 1'b1;
  #200000000 $finish;
end
//My apologies to use two initial blocks. but I guess it gives more
//Structure to the code. As one 'initial' is for reading memory values
//and the other 'initial' block is for assigning values to signals

always #15000 clk = ~clk;


always @ (posedge clk)
begin
  prob = $random;
end


////////////////////////////////////////////////////////////////////////////////
//State Machine Begins
////////////////////////////////////////////////////////////////////////////////
//State Machine Combinational Part
//Instead of using a case statement here, 
//A 'if' statement is delibrately used, to prioritize certain
//Certain possibilites. And since it is just a testbench,
//I would like to take the advantage of if statement
//And Since it is a test bench, I am not worried of priority muxes being
//Synthesized :)
always @ (success or ps or xbytecounter or delaycounter or timeout)
begin
  if(ps == 0)
    ns = 1;
  else if(ps==1 && success == 0 && timeout == 0)
    ns = 1;
  else if(ps==1 && (timeout) && delaycounter == 9 && xbytecounter == totalbytes)
    ns = 2;
  else if(ps==1 && (success) && delaycounter == 9 && xbytecounter == totalbytes)
    ns = 3;
  else if(ps==1 && (success||timeout) && delaycounter==9 && xbytecounter 
                    != totalbytes)
    ns = 2;
  else if(ps == 2 && delaycounter == 17)
    ns = 0;
  else if(ps == 2)
    ns = 2;
  else if (ps == 3)
    ns = 3;
  else if(ps == 7)
    ns = 0;
  else
    ns = 1;
end

//State Machine Sequential Part (i.e) assiging the state register 'ps'
always @ (posedge clk)
begin
  if(reset == 0)
    ps <= 7;
  else
    ps <= ns;
end
////////////////////////////////////////////////////////////////////////////////
//State Machine Ends
////////////////////////////////////////////////////////////////////////////////

//Generate a load signal for the output register when present state is 0
assign load_op_reg = (ps==0)? 1'b1:1'b0;
//Generate a shift for the output register
assign shift_op_reg = (delaycounter==18 && ps != 0 && ps != 3 && 
                       bitcounter != bits_in_one_word+1)? 1'b1:1'b0;

//  The follwing process increments a counter which counts from 0 to 18 and
//  then rolls off to 0.
//  This is to elapse a period of 540us, before which any new bit can be 
//  transmitted.
always @ (posedge clk)
begin
  if(reset == 0) //sync reset of the counter
    delaycounter <= 0;
  else if(delaycounter == 18)
      delaycounter <= 1;
  else if(ps == 0) 
    delaycounter <= 1;
  else
      delaycounter <= delaycounter + 1;
end


// The following procedure increments the 'bitcounter'
// 'bitcounter' is a signal which counts the number of bits transfered.
always @ (posedge clk)
begin
  if(reset == 0)  //sync reset of the counter
    bitcounter <= 0;
  else if(load_op_reg ==1 || shift_op_reg == 1)
  //in case either load_op_reg is 1 or 'shift_op_reg' is one bitcouter must
  //be incremneted if it has not reached its final value of 11.
  //Obviously, when it has reached its final value, it will restart at 1.
    if(bitcounter == bits_in_one_word+1) 
      bitcounter <= 1;
    else
      bitcounter <= bitcounter +1;
  else
    // This line may seem redundant, but it makes better readability of code
    bitcounter <= bitcounter;
end

//  The following procedure increments a counter called 'xbytecounter'
//  xbytecouter counts the number of 'successful' bytes transfered
//  to the receiver
always @ (posedge clk)
begin
  if(reset == 0)  //sync reset of the counter
    xbytecounter <= 0;
  else if(ps == 2 && success == 1 && delaycounter == 10) 
  //delaycounter==10 ensures that xbytecounter counts only once in 540us period
    xbytecounter <= xbytecounter + 1;
end
////////////////////////////////////////////////////////////////////////////////
// Parity Generation Starts
////////////////////////////////////////////////////////////////////////////////
// The following lines of code generates parity.
// Is generated.
// An Intermediate parity is generated called parity_int
// which is then XOR-ed with parity_corr to curroput the parity bit
// Randomly
// 'parity_corr' inverts parity whenever it is '1'
// 'parity_corr' is generated randomly using a signal called 'prob'
// whenever it is > 200.
////////////////////////////////////////////////////////////////////////////////
assign parity_int = ^mem[xbytecounter];
assign parity_corr = (prob>200)? 1'b1:1'b0;
assign parity = (parity_int ^ parity_corr);
////////////////////////////////////////////////////////////////////////////////
// Parity Generation Ends
////////////////////////////////////////////////////////////////////////////////

// Following procedure loads the data to be transmitted into output register
// called 'op_reg' when 'load_op_reg' is '1'
// and also shifts it when 'shift_op_reg' is '1'
always @ (posedge clk)
begin
  if(reset == 0)
    op_reg <= 11'b00000000001;
  else if(load_op_reg == 1) 
    op_reg <= {mystop,parity,mem[xbytecounter],mystart};
  else if(shift_op_reg == 1)
    op_reg <= {op_reg[0],op_reg[bits_in_one_word:1]};
  else 
    op_reg <= op_reg;
end

//Following prodecuder increments the 'timeout counter'
//It starts, at a point where last bit to be transmitted in a data word
//has just been put on the trasmission line

always @ (posedge clk)
begin
  if(ps == 0)
    timeout_counter <= 0;
  else if(ps == 1 && bitcounter == 11)
    timeout_counter <= timeout_counter + 1;
end

//timeout will go high, if a 'success' signal is not received
//and the value of timeout counter reaches 'timeoutcount' which is
//taken to be 50 clock cycles.
assign timeout = (timeout_counter > timeoutcount)? 1'b1:1'b0;

//assign rx_in to op_reg[0] or from a delay register
//the value of xdelay models the dealy in transmission line
//A value of xdelay = 0 means no delay has been modelled
//and rx_in = op_reg[0], where as any other value of
//xdelay can delay the 'rx_in' to 'xdelay' no of clock cycles
assign rx_in = (xdelay)?delay_reg[xdelay]:op_reg[0];


always @ (posedge clk)
begin
  delay_reg[0] <= op_reg[0];
  delay_reg[17:1] <= delay_reg[16:0];
end

//Generate a Modified 'success' signal i.e 'success_mod' which will be
//Used to display the value of 'data_out' on Simulation Log.
always @ (posedge clk)
begin
  if(success == 1 && delaycounter == 11)
    success_mod <= success;
  else
    success_mod <= 0;
end

//Display the value of 'data_out' everytime 'success' is received
always @ (posedge success_mod)
begin
  $display("Time = %0d : data_out = %d", $time,data_out);
end


//Display the value of 'data_out' everytime 'success' is received
always @ (posedge load_op_reg)
begin
  $display("Time = %0d : op_reg[8:1] = %d", $time,mem[xbytecounter]);
end

//Uncomment this prodedure if you want to see a detailed output on console
//always @ (bitcounter or delaycounter)
//begin
//  $display("Time=%0d:reset=%d,delaycounter=%d,ps=%d,bitcounter=%d,xbytecounter=%d,load_op_reg=%d,success=%d,shift_op_reg=%d,timeout=%d,op_reg=%d,rx_in=%d,data_out=%d",$time,reset,delaycounter,ps,bitcounter,xbytecounter,load_op_reg,success,shift_op_reg,timeout,op_reg,rx_in,data_out);
//end


endmodule