LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.numeric_std.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.std_logic_unsigned.ALL; USE std.textio.ALL; USE IEEE.std_logic_textio.ALL; ENTITY ARM_BIST_TB IS GENERIC(period : time := 10 ns; mode_reg_len : integer := 23; --It is important to put this value in 'ns' ONLY. dw_si_so_delay_count : integer := 661 ); --the mode register, when shifted out, takes dw_si_so_delay no of --clock cycles to reach BistTDO. END ENTITY; ARCHITECTURE behav OF ARM_BIST_TB IS --Signal Declaration Section SIGNAL CLK : std_logic := '0'; SIGNAL MMU_CE : std_logic; SIGNAL MMU_WE : std_logic_vector(3 downto 0); SIGNAL MMU_DI : std_logic_vector(111 downto 0); SIGNAL MMU_DO : std_logic_vector(111 downto 0); SIGNAL MMU_A : std_logic_vector(4 downto 0); SIGNAL InstCacheData_CE : std_logic_vector(3 downto 0); SIGNAL InstCacheData_WE : std_logic_vector(3 downto 0); SIGNAL InstCacheData_DI : std_logic_vector(127 downto 0); SIGNAL InstCacheData_DO : std_logic_vector(127 downto 0); SIGNAL InstCacheData_A_Index : std_logic_vector(7 downto 0); SIGNAL InstCacheData_A_3 : std_logic_vector(2 downto 0); SIGNAL InstCacheData_A_2 : std_logic_vector(2 downto 0); SIGNAL InstCacheData_A_1 : std_logic_vector(2 downto 0); SIGNAL InstCacheData_A_0 : std_logic_vector(2 downto 0); SIGNAL InstCacheTAG_CE : std_logic_vector(3 downto 0); SIGNAL InstCacheTAG_WE : std_logic_vector(3 downto 0); SIGNAL InstCacheTAG_DI : std_logic_vector(87 downto 0); SIGNAL InstCacheTAG_DO : std_logic_vector(87 downto 0); SIGNAL InstCacheTAG_A : std_logic_vector(7 downto 0); SIGNAL InstCacheValid_CE : std_logic; SIGNAL InstCacheValid_WE : std_logic; SIGNAL InstCacheValid_DI : std_logic_vector(23 downto 0); SIGNAL InstCacheValid_DO : std_logic_vector(23 downto 0); SIGNAL InstCacheValid_A : std_logic_vector(5 downto 0); SIGNAL DataCacheData_CE : std_logic_vector(3 downto 0); SIGNAL DataCacheData_WE : std_logic_vector(3 downto 0); SIGNAL DataCacheData_DI : std_logic_vector(127 downto 0); SIGNAL DataCacheData_DO : std_logic_vector(127 downto 0); SIGNAL DataCacheData_A_Index : std_logic_vector(6 downto 0); SIGNAL DataCacheData_A_3 : std_logic_vector(2 downto 0); SIGNAL DataCacheData_A_2 : std_logic_vector(2 downto 0); SIGNAL DataCacheData_A_1 : std_logic_vector(2 downto 0); SIGNAL DataCacheData_A_0 : std_logic_vector(2 downto 0); SIGNAL DataCacheTAG_CE : std_logic_vector(3 downto 0); SIGNAL DataCacheTAG_WE : std_logic_vector(3 downto 0); SIGNAL DataCacheTAG_DI : std_logic_vector(87 downto 0); SIGNAL DataCacheTAG_DO : std_logic_vector(87 downto 0); SIGNAL DataCacheTAG_A : std_logic_vector(7 downto 0); SIGNAL DataCacheValid_CE : std_logic; SIGNAL DataCacheValid_WE : std_logic; SIGNAL DataCacheValid_DI : std_logic_vector(23 downto 0); SIGNAL DataCacheValid_DO : std_logic_vector(23 downto 0); SIGNAL DataCacheValid_A : std_logic_vector(4 downto 0); SIGNAL DataCacheDirty_CE : std_logic; SIGNAL DataCacheDirty_WE : std_logic_vector(7 downto 0); SIGNAL DataCacheDirty_DI : std_logic_vector(7 downto 0); SIGNAL DataCacheDirty_DO : std_logic_vector(7 downto 0); SIGNAL DataCacheDirty_A : std_logic_vector(6 downto 0); SIGNAL Isolate : std_logic; SIGNAL TestBIST : std_logic; SIGNAL TestEMARam : std_logic_vector(2 downto 0); SIGNAL TestEMA : std_logic_vector(2 downto 0); SIGNAL TestRAM : std_logic; SIGNAL TestShadow : std_logic; SIGNAL ScanEnable : std_logic; SIGNAL ScanIn : std_logic_vector(63 downto 0); SIGNAL ScanOut : std_logic_vector(63 downto 0); SIGNAL BistResetN : std_logic; SIGNAL BistTRSTn : std_logic; SIGNAL BistTCK : std_logic := '0'; SIGNAL BistTDI : std_logic; SIGNAL BistTDO : std_logic; SIGNAL shift_dr : std_logic; SIGNAL BistRun : std_logic; --tb signals SIGNAL tb_counter : integer := 0; SIGNAL mode_reg : std_logic_vector(mode_reg_len-1 downto 0); SIGNAL mode_reg_captured : std_logic_vector(mode_reg_len-1 downto 0); --For more info on programming mode reg or any info --related to it Pls refer to the synopsys DW_rambist document at: -- \\dserve2\doc\205 DES\Production Test\syn_DW_rambist_databook.pdf CONSTANT count_7ms : integer := 7000000/(period/1 ns); CONSTANT count_6_5ms : integer := 6500000/(period/1 ns); CONSTANT count_6ms : integer := 6000000/(period/1 ns); CONSTANT count_5_5ms : integer := 5500000/(period/1 ns); CONSTANT count_5ms : integer := 5000000/(period/1 ns); CONSTANT count_1us : integer := 1000/(period/1 ns); CONSTANT dw_si_so_delay : integer := dw_si_so_delay_count; --the mode register, when shifted out, takes dw_si_so_delay no of --clock cycles to reach BistTDO --Signal Declaration Section Ends COMPONENT ARM_RAM_WRAPPER PORT ( CLK : IN std_logic; MMU_CE : IN std_logic; MMU_WE : IN std_logic_vector(3 downto 0); MMU_DI : IN std_logic_vector(111 downto 0); MMU_DO : OUT std_logic_vector(111 downto 0); MMU_A : IN std_logic_vector(4 downto 0); InstCacheData_CE : IN std_logic_vector(3 downto 0); InstCacheData_WE : IN std_logic_vector(3 downto 0); InstCacheData_DI : IN std_logic_vector(127 downto 0); InstCacheData_DO : OUT std_logic_vector(127 downto 0); InstCacheData_A_Index : IN std_logic_vector(7 downto 0); InstCacheData_A_3 : IN std_logic_vector(2 downto 0); InstCacheData_A_2 : IN std_logic_vector(2 downto 0); InstCacheData_A_1 : IN std_logic_vector(2 downto 0); InstCacheData_A_0 : IN std_logic_vector(2 downto 0); InstCacheTAG_CE : IN std_logic_vector(3 downto 0); InstCacheTAG_WE : IN std_logic_vector(3 downto 0); InstCacheTAG_DI : IN std_logic_vector(87 downto 0); InstCacheTAG_DO : OUT std_logic_vector(87 downto 0); InstCacheTAG_A : IN std_logic_vector(7 downto 0); InstCacheValid_CE : IN std_logic; InstCacheValid_WE : IN std_logic; InstCacheValid_DI : IN std_logic_vector(23 downto 0); InstCacheValid_DO : OUT std_logic_vector(23 downto 0); InstCacheValid_A : IN std_logic_vector(5 downto 0); DataCacheData_CE : IN std_logic_vector(3 downto 0); DataCacheData_WE : IN std_logic_vector(3 downto 0); DataCacheData_DI : IN std_logic_vector(127 downto 0); DataCacheData_DO : OUT std_logic_vector(127 downto 0); DataCacheData_A_Index : IN std_logic_vector(6 downto 0); DataCacheData_A_3 : IN std_logic_vector(2 downto 0); DataCacheData_A_2 : IN std_logic_vector(2 downto 0); DataCacheData_A_1 : IN std_logic_vector(2 downto 0); DataCacheData_A_0 : IN std_logic_vector(2 downto 0); DataCacheTAG_CE : IN std_logic_vector(3 downto 0); DataCacheTAG_WE : IN std_logic_vector(3 downto 0); DataCacheTAG_DI : IN std_logic_vector(87 downto 0); DataCacheTAG_DO : OUT std_logic_vector(87 downto 0); DataCacheTAG_A : IN std_logic_vector(7 downto 0); DataCacheValid_CE : IN std_logic; DataCacheValid_WE : IN std_logic; DataCacheValid_DI : IN std_logic_vector(23 downto 0); DataCacheValid_DO : OUT std_logic_vector(23 downto 0); DataCacheValid_A : IN std_logic_vector(4 downto 0); DataCacheDirty_CE : IN std_logic; DataCacheDirty_WE : IN std_logic_vector(7 downto 0); DataCacheDirty_DI : IN std_logic_vector(7 downto 0); DataCacheDirty_DO : OUT std_logic_vector(7 downto 0); DataCacheDirty_A : IN std_logic_vector(6 downto 0); Isolate : IN std_logic; TestBIST : IN std_logic; TestEMARam : IN std_logic_vector(2 downto 0); TestEMA : IN std_logic_vector(2 downto 0); TestRAM : IN std_logic; TestShadow : IN std_logic; ScanEnable : IN std_logic; ScanIn : IN std_logic_vector(63 downto 0); ScanOut : OUT std_logic_vector(63 downto 0); BistResetN : IN std_logic; BistTRSTn : IN std_logic; BistTCK : IN std_logic; BistTDI : IN std_logic; BistTDO : OUT std_logic; shift_dr : IN std_logic; BistRun : IN std_logic ); END COMPONENT; -- my_decoder BEGIN ARM_RAM_WRAPPER_I0:ARM_RAM_WRAPPER PORT MAP ( CLK => CLK, MMU_CE => MMU_CE, MMU_WE => MMU_WE, MMU_DI => MMU_DI, MMU_DO => MMU_DO, MMU_A => MMU_A, InstCacheData_CE => InstCacheData_CE, InstCacheData_WE => InstCacheData_WE, InstCacheData_DI => InstCacheData_DI, InstCacheData_DO => InstCacheData_DO, InstCacheData_A_Index => InstCacheData_A_Index, InstCacheData_A_3 => InstCacheData_A_3, InstCacheData_A_2 => InstCacheData_A_2, InstCacheData_A_1 => InstCacheData_A_1, InstCacheData_A_0 => InstCacheData_A_0, InstCacheTAG_CE => InstCacheTAG_CE, InstCacheTAG_WE => InstCacheTAG_WE, InstCacheTAG_DI => InstCacheTAG_DI, InstCacheTAG_DO => InstCacheTAG_DO, InstCacheTAG_A => InstCacheTAG_A, InstCacheValid_CE => InstCacheValid_CE, InstCacheValid_WE => InstCacheValid_WE, InstCacheValid_DI => InstCacheValid_DI, InstCacheValid_DO => InstCacheValid_DO, InstCacheValid_A => InstCacheValid_A, DataCacheData_CE => DataCacheData_CE, DataCacheData_WE => DataCacheData_WE, DataCacheData_DI => DataCacheData_DI, DataCacheData_DO => DataCacheData_DO, DataCacheData_A_Index => DataCacheData_A_Index, DataCacheData_A_3 => DataCacheData_A_3, DataCacheData_A_2 => DataCacheData_A_2, DataCacheData_A_1 => DataCacheData_A_1, DataCacheData_A_0 => DataCacheData_A_0, DataCacheTAG_CE => DataCacheTAG_CE, DataCacheTAG_WE => DataCacheTAG_WE, DataCacheTAG_DI => DataCacheTAG_DI, DataCacheTAG_DO => DataCacheTAG_DO, DataCacheTAG_A => DataCacheTAG_A, DataCacheValid_CE => DataCacheValid_CE, DataCacheValid_WE => DataCacheValid_WE, DataCacheValid_DI => DataCacheValid_DI, DataCacheValid_DO => DataCacheValid_DO, DataCacheValid_A => DataCacheValid_A, DataCacheDirty_CE => DataCacheDirty_CE, DataCacheDirty_WE => DataCacheDirty_WE, DataCacheDirty_DI => DataCacheDirty_DI, DataCacheDirty_DO => DataCacheDirty_DO, DataCacheDirty_A => DataCacheDirty_A, Isolate => Isolate, TestBIST => TestBIST, TestEMARam => TestEMARam, TestEMA => TestEMA, TestRAM => TestRAM, TestShadow => TestShadow, ScanEnable => ScanEnable, ScanIn => ScanIn, ScanOut => ScanOut, BistResetN => BistResetN, BistTRSTn => BistTRSTn, BistTCK => BistTCK, BistTDI => BistTDI, BistTDO => BistTDO, shift_dr => shift_dr, BistRun => BistRun ); BistTCK <= not(BistTCK) after ((period/2 ns) * 1 ns ); CLK <= not(CLK) after ((period/2 ns) * 1 ns ); TestBIST <= '1' ; TestEMARam <= (others => '0'); TestEMA <= (others => '0'); TestRAM <= '0'; TestShadow <= '0'; --ScanIn <= (others => '0'); ScanEnable <= '0'; Isolate <= '0'; counter_p : process(CLK) begin if(rising_edge(CLK)) then tb_counter <= tb_counter + 1; end if; end process counter_p; program_mode_reg_p : process(CLK) begin if(rising_edge(CLK)) then if(tb_counter = 0) then BistResetN <= '0'; BistTRSTn <= '0'; shift_dr <= '0'; BistRun <= '0'; BistTDI <= '0'; mode_reg <= "11111111000000000111110"; end if; if(tb_counter = count_1us-1) then BistResetN <= '1'; BistTRSTn <= '1'; end if; if(tb_counter >= count_1us and (tb_counter < (count_1us + mode_reg'length))) then shift_dr <= '1'; BistTDI <= mode_reg(mode_reg'high); mode_reg <= mode_reg((mode_reg'high)-1 downto 0) & mode_reg(mode_reg'high); end if; if(tb_counter = count_1us + (mode_reg'length)) then shift_dr <= '0'; BistRun <= '1'; end if; --Wait for 5.5 ms i.e the time when bist would have finished, and retention --test started --After 5.5 ms --Shift in '0' inside bit 6 of mode register which should have gone '1' by now --to continue with retention testing. if(tb_counter >= count_5_5ms and (tb_counter < (count_5_5ms + mode_reg'length))) then shift_dr <= '1'; BistRun <= '0'; BistTDI <= mode_reg(mode_reg'high); mode_reg <= mode_reg((mode_reg'high)-1 downto 0) & mode_reg(mode_reg'high); end if; --Stop Shifting, continue Bist RUN let it run for say 500us if(tb_counter = count_5_5ms + (mode_reg'length)) then shift_dr <= '0'; BistRun <= '1'; end if; -- After 500us, -- Shift in '0' inside bit 6 of mode register which should have AGAIN gone '1' by now -- to continue with retention testing. if(tb_counter >= count_6ms and (tb_counter < (count_6ms + mode_reg'length))) then shift_dr <= '1'; BistRun <= '0'; BistTDI <= mode_reg(mode_reg'high); mode_reg <= mode_reg((mode_reg'high)-1 downto 0) & mode_reg(mode_reg'high); end if; --Stop Shifting, continue Bist RUN for say another 500us if(tb_counter = count_6ms + (mode_reg'length)) then shift_dr <= '0'; BistRun <= '1'; end if; --Wait for 6.5 ms for bist to finish --Then deassert BistRun, assert shift_dr with an intention to shift out --the value in Mode Register if(tb_counter >= count_6_5ms and (tb_counter < (count_6_5ms + dw_si_so_delay))) then shift_dr <= '1'; BistRun <= '0'; end if; if((tb_counter >= count_6_5ms + dw_si_so_delay) and (tb_counter < (count_6_5ms + dw_si_so_delay + (mode_reg_captured'length)))) then mode_reg_captured(0) <= BistTDO; mode_reg_captured(mode_reg_captured'high downto 1) <= mode_reg_captured(mode_reg_captured'high-1 downto 0); end if; if(tb_counter = (count_6_5ms + dw_si_so_delay+mode_reg_captured'length)) then shift_dr <= '0'; end if; end if; end process program_mode_reg_p; report_pass_fail_p : process(CLK) begin if(rising_edge(CLK)) then if(tb_counter = (count_6_5ms + dw_si_so_delay + (mode_reg_captured'length) + 1)) then if(mode_reg_captured(0) /= '1') then assert FALSE report "End of Sim : Bist Sim Failed, mode_reg(0) is not '1'" severity Failure; else assert FALSE report "NONE: End of Sim : Bist Sim Passed, mode_reg(0) is '1'" severity Failure; end if; end if; end if; end process report_pass_fail_p; END behav; library arm926ejs_wrap_bist_temp; configuration armbist_gates_config of arm_bist_tb is for behav for all : ARM_RAM_WRAPPER use entity arm926ejs_wrap_bist_temp.ARM_RAM_WRAPPER; end for; end for; end configuration armbist_gates_config;