library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.ALL;
USE ieee.std_logic_textio.ALL;

entity overall is
    Port ( data_in : in  STD_LOGIC_VECTOR(3 DOWNTO 0);
           clk : in  STD_LOGIC;
           data_out : out  STD_LOGIC_VECTOR(3 DOWNTO 0);
			 write_data: in std_logic
	             );
end overall;

architecture Behavioral of overall is

component sample
Port ( 		ain : in  STD_LOGIC_VECTOR(3 DOWNTO 0);
				clk : in  STD_LOGIC;
				b : out  STD_LOGIC_VECTOR(3 DOWNTO 0)
		);
end component;

component mem
	port (
	a: IN std_logic_VECTOR(3 downto 0);
	d: IN std_logic_VECTOR(3 downto 0);
	clk: IN std_logic;
	we: IN std_logic;
	spo: OUT std_logic_VECTOR(3 downto 0));
end component;

attribute syn_black_box : boolean;
attribute syn_black_box of mem: component is true;

signal address: std_logic_vector(3 downto 0);
signal transfer: std_logic_vector(3 downto 0);

begin

mapsample : sample
		port map (
			ain => data_in,
			clk => clk,
			b =>	transfer);

your_instance_name : mem
		port map (
			a => address,
			d => transfer,
			clk => clk,
			we => write_data,
			spo => data_out);
			
process (clk,write_data)
begin
	if clk'event and clk = '1' then
		if write_data = '1' then address <= address + 1;
		else
			address <= "0000";
		end if;
	end if;

end process;

write_file_p : process(clk)
  file f1 : TEXT IS OUT "./data.txt";
  variable address_var : std_logic_vector(3 downto 0);
  variable l1 : line;
begin
  if(clk'event and clk = '1') then
    address_var := address;
    if(write_data = '1') then
      write(l1,address_var);
      --hwrite(l1,address_var); -- uncomment and use this line if you have to write hex instead of binary
      write(l1,' '); --optional to write a space character
      write(l1,now); --optional to write the current simulation time
      writeline(f1,l1);
    end if;
  end if;
end process write_file_p;

end Behavioral;