Library ieee;
use ieee.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

entity nosen is
port (
       clk : in std_logic;
       rst : in std_logic;
       ain : in std_logic;
       bin : in std_logic;
       bout : out std_logic;
       dat_in : in std_logic_vector(3 downto 0);
       dat_out : out std_logic_vector(3 downto 0)

     );
end entity;
architecture trial of nosen is
signal dat_out_sig : std_logic_vector(3 downto 0);
signal bsig : std_logic;
begin
count_p:  process(clk)
  begin
  if(rising_edge(clk)) then
    if(rst='1') then
      dat_out_sig <= (others => '0');
    else
      dat_out_sig <= dat_out_sig + 1;
    end if;
  end if;
end process count_p;

comb_p : process
begin
bsig <= '0';
bout <= '0';
  if(dat_out_sig = 4) then
    bsig <= '1';
  end if;
  if(bsig = '1') then
    bout <= '1';
  end if;
end process comb_p;
dat_out <= dat_out_sig;
end trial;