A signal called 'dump' may be forced anytime during the simulaiton
to dump out the memory contents into a text file called myram.dat

Download it as a .vhd file here:

--Generated by genEntity.pl Report Problems to avimit on yahoo dat com
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all ;
--translate_off
use ieee.std_logic_textio.all;

library std;
use std.textio.all;
--translate_off

ENTITY myram IS
  GENERIC( dwidth : integer := 8;
           awidth : integer := 8
         );
  PORT (
    clk : in std_logic;
    wen : in std_logic;
    rd_addr : in std_logic_vector(awidth-1 downto 0);
    wr_addr : in std_logic_vector(awidth-1 downto 0);
    di : in std_logic_vector(dwidth-1 downto 0);
    qq : out std_logic_vector(dwidth-1 downto 0)
  );
END myram;

ARCHITECTURE rtl OF myram IS
--SIGNAL Declaration Section Starts
  type mem_array is array(2**awidth -1 downto 0) of std_logic_vector(dwidth-1 downto 0);
  SIGNAL mem_data : mem_array;
  SIGNAL dump : std_logic := '0'; --a 0 to 1 transition on this signal
  --dumps the entire memory in a text file called myram.dat
  --SIGNAL mem_data : mem_array := (others => (others => '0'));
--SIGNAL Declaration Section Ends

--translate_off
  CONSTANT prefix : string := "myram";
  CONSTANT extn   : string := ".dat";
--translate_on

  BEGIN
sync_reset_p : PROCESS(clk)
  BEGIN
  IF(rising_edge(clk)) then
    if(wen = '1') then
      mem_data(conv_integer(wr_addr)) <= di;
    end if;
  END IF;
END process sync_reset_p;
qq <= mem_data(conv_integer(rd_addr));
 

--translate_off
dump_p : process(dump)
file fout    : text is out prefix & extn;
--file fout : text is out  prefix & extn;
variable l1 : line;
begin
  if(rising_edge(dump)) then
    for ii in 0 to 2**awidth-1 loop
      write(l1,ii);
      write(l1,' ');
      write(l1,mem_data(ii));
      writeline(fout,l1);
    end loop;
  end if;
end process dump_p;
--translate_on

END rtl;