LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity myadder is --this line describes an 'entity' named 'myadder'
  port
  (
     -- input ports
     a : in std_logic; -- this line describes a 'port' named 'a' with its direction as 'input' and is of type 'std_logic'
     b : in std_logic;
     c_in : in std_logic;

     -- output ports
     sum : out std_logic;
     c_out : out std_logic
  );
end entity;

architecture func_description of myadder is -- this line describes the name of architecture i.e 'func_description' of a entity called 'myadder'
begin
  add_desc_comb_p : process(c_in,a,b) -- this line describes a 'process' which has 'c_in,a,b' in its 'sensitivity list' and which has been labeled as 'add_desc_comb_p'
  begin
    sum <= 'X';
    c_out <= 'X';
    If (c_in = '0' and a = '0' and b = '0' ) then
        sum <= '0';
        c_out <= '0';
    end if;
    If(c_in = '0' and a = '0' and b = '1') then
        sum <= '1' ;
        c_out <= '0';
    end if;
    If(c_in = '0' and a = '1' and b = '0' ) then
        sum <= '1' ;
        c_out <= '0';
    end if;
    If(c_in = '0' and a = '1' and b = '1' ) then
        sum <= '0';
        c_out <= '1';
    end if;
    If(c_in = '1' and a = '0' and b = '0' ) then
        sum <= '1' ;
        c_out <= '0';
    end if;
    If(c_in = '1' and a = '0' and b = '1' ) then
        sum <= '0';
        c_out <= '1';
    end if;
    If(c_in = '1' and a = '1' and b = '0' ) then
        sum <= '0';
        c_out <= '1';
    end if;
    If(c_in = '1' and a = '1' and b = '1' ) then
        sum <= '1' ;
        c_out <= '1';
    end if;
  end process add_desc_comb_p;
end func_description;