VHDL Vs Verilog:
Author: Aviral Mittal
email: vlsiip@vlsiip.com

Although both of these languages are used to design hardware, each of them have got
distinct features, which makes them better than the other. But I am not a fan of verilog,
and I think that one should use VHDL for RTL because of the following reasons.
I would be very happy if someone can give answers to the following verilog

1). Writing a Function:
Verilog fails badly. For example consider the following function 'incr_vec' which takes
a vector and returns 'vector+1'. VHDL could write this function so easily.
But is there anyone who could write a equivalent function in verilog?

FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is
              --this function increments a std_logic_vector type
    VARIABLE V : std_logic_vector(s1'high downto s1'low) ;
    VARIABLE tb : std_logic_vector(s1'high downto s1'low);
    tb(s1'low) := en;
    V := s1;
    for i in (V'low + 1) to V'high loop
        tb(i) := V(i - 1) and tb(i -1);
    end loop;
    for i in V'low to V'high loop
        if(tb(i) = '1') then
            V(i) := not(V(i));
        end if;
    end loop;
    return V;
    end incr_vec; -- end function

Notice the use of 'high and 'low to cope with the 'width' of the input vector.

2). Writing structural Code:
Verilog again Fails.
VHDL has a very powerful statement called 'GENERATE' which can be used to
generate structural codes very efficiently.

3). Arrays:
Verilog does not have anything like multi dimentional arrays. Of course you can write something like
reg [width:0] mem[size:0]
but then this signal cannot be used in sensitivity list of a process, and there is a potential risk of simulation
vs synthesis simulation mismatches.
Hence verilog fails.
4). VHDL supports something called structures. Which are just like C language structures
Verilog doesn't have anything which can represent C-structures.

Now there might be things in verilog which cannot be done eaisly in VHDL, but I am not aware of any
thing that cannot be done at all.

Hence I would not recommend the use of Verilog while writing RTL.