Connect @ https://www.linkedin.com/in/avimit/ Aviral Mittal

AHB and AXI both has a burst kind called 'WRAP'
What does it mean, and why it is there, and how it is used?

AHB WRAP burst 'wraps' around Burst Boundary.
Let us see an example.
The burst is WRAP 4. HSIZE = '010' (32 bit word Accesses)
and the start address is 0x1018, then the burst addresses will be:
0x1010 (instead of 0x1020)
0x1014 (instead of 0x1024)
because the burst will wrap around the burst boundary at 0x001F, also called block size boundary.
Wrap boundary or block size is determined by the Size of transfer * Beat length.
Size of transfer = 2^(HSIZE) i.e = 1, for HSIZE = 0, 2 for HSIZE = 1, 4 for HSIZE = 2, 8 for HSIZE = 3.....
Beat Length = 4, for WRAP4, 8 for WRAP8, and 16 for WRAP16.

So why would someone want issue WRAP Burst.
WRAP burst are suitable for filling up the cache lines.
For example if the cache line is 16 bytes, i.e 4 32 bit words, then if the processor issues a fetch from starting
address 0x1018 and this address is a miss,
then the data sought by the cache controller will be the data from
Now if the cache controller issues INCR4 to get the above data, the processor will have
to wait till the data from 0x1018 becomes available.

Whereas if the cache controller issues WRAP4 is issued starting 0x1018,
then the data corresponding to the above 4 addresses will be
fetched, but the first data will be from 0x1018, which the processor actually wanted to start with, and
then the processor wont have to wait.
This is also called 'critical-word-first' fill scheme.
And without WRAP burst support, the cache controller might just issue an INCR4 burst starting at 0x1010.
And then the processor will un-neccessarily wait till the contents of location 0x1018 becomes available.

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KeyWords: AHB Issues, AHB Locked transfers. HLOCK, HMASTLOCK, bit-banding. Read-modify-write. bit band