Random Info ARM Cortex M0


M0 12K Gates 16uW/MHz : on what technology?
16 Bit thumb instructions for lower code density
Supports only 56 base instructions
Load-store Architecture
3 Stage Pipeline: Fetch-Decode-Execute
3 instructions are handled concurrently.
NVIC : 32 Interrupts and and NMI
Supports WIC
WIC masks Interrupt signals while processor is in sleep mode. WIC is only active when processor is in DEEPSLEEP mode?? really I thought for M0 it is available for SLEEP mode as well.
32 bit wide bus
AHB Lite.
Instruction processing is suspended when a debug event takes place
And the debug block allows the execution of 1 instruction at a time
in order to observe how the registers and memory change.

16 GP registers.
13 are for GP uses.
R13 -> Stack Pointer -> MSP, (Main Stack Pointer), PSP. PSP is for privileged access.
R14 -> Link Register
R15 -> Program Counter.

Special Regs:
xPSR -> APSRApplication PSR, EPSR Execution PSR, IPSR Interrupt PSR
Interrupt Mask Register -> also called PRIMASK register. 1 bit register, when set it blocks all inters except nmi. It is accessed using special register access instructions mrs and cps, cps=change processor state.
Stack Definition Control register
Word -> 32 bits
byte and 1/2 words are loaded into 32 bit internal registers while processing.
R0->R7 can be accessed by any instruction
R8->R12 : some may not be accessed by some thumb instructions.

PC is sometimes uses as a pointer to access constants.

Link Register is automatically loaded with the return address whenever a sub-routine is called.

MSP/PSP at reset

M0 memory map, some addresses are considered executable, namely 0x0000_0000 -> 0x3FFF_FFFF, 0x6000_0000->09FFF_FFFF.
This means the instructions can be fetched and executed from these addresses.
If you try to execute an instruction from a place which is not in executable region, it will cause a fault.?? why how??

The Code region is usually on-chip memory used to store program code. It can also be used for data.

The 'peripheral' region from 0x4000_0000 to 0x5FFF_FFFF is primarily meant for on-chip peripherals,
where as the External device region from 0xA000_0000 to 0xDFFF_FFFF is meant for off chip peripherals. (SD-CARDS).

SYSTIC timer is used for RTOS.

Cortex-M0 instructions: total 56.

Thumb1 reduced ~30%, but performance is also reduced by ~20%
Thumb 2 ~26% code size reduction at same performance.

M0 instruction set 50 Thumb1 16 bit instructions, 6 32 bit thumb 2 instructions.

ADD r0,r1,r2 = r0 = r1+r2;

r2 can be a constant.

r1 is destination. constant is immediate value, which is embedded in the code. # is used to signify that the value is a immediate value.
r2 can be a source register.
MOV is only register
Mem is accessed by load/store instructions.
in Load instructions, the address register is inside [] eg [R2].
no direct mem operations. The data must be copied using load instruction inside a register then operated upon then stored back.

LDR R0, [R1,4] -> load value at an address R1 + 4 into R0
LDR R0, [R1,R2] -> load a value at an address R1 + R2 into R0.

LDR R0,=0x12345678. Load immediate value 0x12345678 into R0.

Sign extension

Similarly : Store : STR, STRH, STRB,
STMIA R0, {R1,R2-R7} Store multiple registers,

LDM: multiple load
LDM R0, {R1,R2=R7} -> r1 gets the value from [R0], r2 gets the value from [r0+4], r3 gets the value form r0+8 and and so on.
LDMIA, load and then adjust the [R0] to point to last address after all registers.

Question: M0 does not support burst, so this means that above are several SINGLE operations? I will guess so.

use PUSH to push into stack, with stack pointer holding the address.
ADDS add with updating APSR
ADD wont update the APSR.
ADC -> carry

SUBS R0,R1,R2 => R0 = R1 - R2, Update APSR
SUBS R0,R1,#0x01 => R0 = R1 - 0x01, update APSR
SBCS R0,R0,R1 => R0 = R0-R1-Borrow, update APSR.
RSBS R0,R0,#0  => R0 = -R0 (Reverse Subtract (negative) Update APSR,

MULS R0,R01,R0 R0 = R1xR0, update APSR.

CMP R0,R1, update flags in APSR, the result of comparision is not stored. Compare is done using subtraction, but the subtraction result is not stored.
CMN : R0,R1: compare negative of R1, update apsr.

ANDS, Logical AND, Update APSR
ORRS Logical OR, update APSR
EORS Logical XOR, update APSR
MVNS : logical Bitwise Not, update APSR
BICS : logical Bitwise Clear, upate APSR
TST : Test (bitwise AND), calculate AND (Rd,Rm), update the APSR but the AND result is not stored. TST R0,R1 => Calculate AND (R0,R1), update APSR.

ASRS Arithematic shift, update APSR. ASRS R0,R1 => R0 = R0 >> R1.
ASRS R0,R1,#0x01 => R0 = R1 >> 1, update APSR.

LSRS logic shift right, logical right shift by number of bits indicated by register R1.
LSLS logic shift left

RORS rotate only one rotate instruction. C flag updated. RORS R0,R1 => Rotate R0 by number of bits indicated by R1, update APSR. (c flag). N and Z flags are also set for negative or zero result.

Data re-ordering instruction
REV, reverse order of bytes.
REV15 byte order revers
REVSH byte order reverse within lower half word, then sign extend result.
these are to support the endian-ness changes i.e little endian to big endian etc.

SXTB : sign extend lowest byte in a word of data, copying bit 7 SXTB R0,R1 => R0 = signExtend(R1[7:0])
SXTH: Sign extend lower half word in a word of data
UXTB Unsign extend lowest byte.
UXTH unsign extend lower half word. UXTH R0,R1 => R0=ZeroExtend(R1[15:0])

control flow instructions:
B <label> Branch to an address unconditional e.g. B loop
B <cond> <label>  Conditional branch, depending upon APSR e.g. BEQ, if APSR.Z - 1, then ...
BL label : branch and link. Store return address in LR e.g. BL myfunction; => Change PC to the address with label of 'myfunction', LR = PC + 4;
BX <Rm> Branch and exchange. Branch to an address specified by register, and change processor state (Arm or Thumb) depending upon Bit[0] of the register e.g. BX R0 => PC = R0
BLX. Branch and link with exchange. e.g. BX R0.

For conditional branch instructions the condition can be one of 14 possible
EQ equal            APSR.Z = 1
NE not equal,       APSR.Z = 0
CS carry set        APSR.C = 1
CC Carry Clear      APSR.C = 0
MI Negative         APSR.N = 1
PL Positive         APSR.N = 0
VS Overflow         APSR.V = 1
VC No Overflow      APSR.V = 0
HI Unsigned Higher               APSR.C  = 1 and APSR.Z = 0
LS Unsigned Lower or same        APSR.C  = 0 or APSR.Z = 1
GE Signed greater than or equal  APSR.N  = APSR.V
LT Signed less than              APSR.N != APSR.V
GT Signed greater than          (APSR.Z = 0) and (APSR.N  = APSR.V)
LE Signed less than or equal    (APSR.Z = 1) or  (APSR.N != APSR.V)

Example coding : BGT loop; => branch to loop if R0 is greater than (GT) 1.

Memory instructions, supported by M0.
DMB : Data memory barrier, ensures that all memory accesses are completed before new memory access is committed.
DSB : Data synh barrier, ensures that all memory accesses are completed before the next instruction is executed.
ISB : Instruction sync barrier, Flushes the pipeline and ensures that all previous instructions are completed before executing new instructions.

Exception related instructions:
SVC <imme 8 bit> Supervisor Call, Trigger the SVC exception. e.g. SVC #3, trigger SVC exception with parameter = 3, indicates which system service is required.
CPS Change processor state. Enable/Disable Intrrupt, does not block NMI and hard fault handler e.g. CPSIE I (Enable Interrupt clearing PRIMASK), CPSID I Disable Interrupt setting PRIMASK.

BKPT imme Breakpoint during debug, the processor is halted. Usually the BKPT is inserted by the debugger to replace the original instruction. An 8 bit imme data can be used as an identifier.
YEILD Indicates task is stalled, currently its a NOP on M0

Sleep mode instructions:
WFI: affected by debug enable. Stops program execution, until an interrupt arrives or until the processor enters debug state.
WFE : wait for event, same as above, but also sensitive to certain events.
SEV: Send event to all processors in a multiprocessor system.

DMIPS/mW measure of energy efficiency.

Sleep-on-Exit: mainly used for interrupt driven applications: Processor enters sleep mode after completing execution of all Interrupt handlers. Enabled by system control register.