System on Chip Architecture Tutorial
-Aviral Mittal

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QSPI I/F on Microcontrollers.
Micro-controllers typically will have most of the code storage in off chip Flash memory. The flash memory may be accessed by a SPI/QSPI/OSPI I/F on the SoC.
These interfaces are frequency limited as they go off chip. Typical range of working can be low 10s of MHz to 200 MHz max today (Feb 2021).
The accesses to the memory devices are serial in nature.
1. Assert Chip Select
2. Send Command
3. Send Start address of the data
4. Send Mode bits
5. Send Dummy bytes for required time delay before data access.
6. Get/Put as much data as desired starting from the 'start address'. Entire memory array can be fetched/Stored
7. If  jump to a non-serial different address is required, De-assert the Chip select and then Go to Step 1. Certain devices may allow to skip the sending of the command phase, if the device is programmed to do so. This will help as while making a address jump, less serial 'rituals' will be needed which will save time and power.

Note that the SPI/QSPI/OSPI I/F can work in DDR (double data rate) mode. In this mode, both edges of the clock are used, which doubles the data transfer bandwidth.

The SPI/QSPI/OSPI I/F may also be used to access off chip PSRAM (pseudo static ram), sometimes its also called Cellular RAM. However PS-RAM is volatile, if power is off, data is lost. PSRAM is suited for expanding the on-chip RAM for applications which require more memory.
PSRAM has many synonyms : IoT RAM, Cellular RAM, FCRAM (Fast Cycle Ram)
PSRAM is a compromise. It typically has higher costs then SDRAM, but these have less access latencies than SDRAM. As compared to on chip RAMs of course PSRAM is slow, but cheaper. As compared to Flash, its going to be way faster.

Note that PSRAM typically has SRAM I/F, but these are also produced with QSPI/OSPI I/Fs to make them compatible with Flash Interfaces. In Microcontroller world this provides pin saving advantages, as single QSPI/OSPI I/F can be shared with 2 difference devices (1) Flash and (2) PSRAM, by using a difference 'Chip Select' signal for the device.

Apparently the HyperRAM has lower stand-by power consumption than PSRAM, it can use the same OSPI I/F. The Operation Power appears the same between HyperRam and PSRAM. However the HyperRam has a differential clock requirement for 1.8V version as per cypress.

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