Ever Wondered, while writing a testbench or while doing a simulation, you drive the AXI Port, but the system either hangs,
or nothing pops out from the other side.
For example let us take a AXI2AHB bridge.
The AXI Port is being driven, but nothing pops out from the AHB side.
I have encountered this situation a couple of times.
These are things you need to check:
1. First and foremost, clk and reset : check both sides.
2.Check the clock relationship between both sides. Try with same clock on both sides first, even if the bridge is Async.
3.If you are doing a write, both write channels i.e. the AW, and W channels are working in tandem.
4. From the AXI driver or master side, check the ready/valid pairs
5. Check WSTROBE: This is imp: if WSTROBE is 0, then the system may hang
6. Check the AWSIZE, AWLEN signals.
7. Check the other side valid/ready signals. The other side should be able to drain/Accept the transactions
8. If the other side is AHB, very imp to check HREADY and HSEL signals. Both shd be '1'.

9. Another common thing is to noice that if the other side is AHB, the AHB address does not increase. This may be
    because of AXI AWBURST/ARBURST = FIXED (00). Change it to INCR(01), and the AHB addresses will start increasing.

10. By definition and spec, the AXI protocol only requires the first or the start address of the transaction to be issued.
      The length of transaction is then determined by AWLEN/ARLEN. The number of bytes in transfer will depend upon
      strobe and AxSize signals.

11. Check the Size signals. If you put wrong value of Size, the Simulation may not produce desired results.
For example if your data bus width is 32 bits (4 bytes) and if you put awsize = 3'b011. Simulation will not work
For 32 bit bus awsize must be = 3'b010