is in general used in connection to netlist
simulations and STA where the propagation delay(s)
through each cell in the netlist
is overridden by the delay value(s) specified in a special file
called sdf(synopsys delay format) file. The process of putting delays
from a given source for the
cells in a netlist
simulation is called Back Annotation. Normally the values of the
delays corresponding to each cell in the netlist
would come from the simulation library i.e verilog
model of library cells. But those delays are not the actual delays of
cells, as each of them is instantiated
in a netlist
in different surroundings, different physical locations, different
loads, different fan in.
The delay of two similar cells in the netlist
at two different physical locations in a chip can be significantly
different depending upon above said factors. Therefore in order to have
actual delays for the cells
in your netlist,
an SDF is written out, by a EDA tool can be a synthesis tool or a
layout tool etc..
which contains the delays of each instance of each library cell
in the netlist,
under the circumstances the cell is in.
During simulations or Static Timing Analysis, each cell in the netlist
gets its correponding delay read, or more
technically 'annotated' from the SDF file.
SDF file contains the delay value of each timing arc
corresponding to each cell in the netlist.
These delay values in the SDF file are extracted
under a given conditions of the netlist.
It may be that the SDF corresponds to just an after
with wire loads estimated according to some wire load model, or it may
be that the SDF corresponds to a neltist
which has been laid out, with actual position of cell,
actual load on the cell, actual metal wires connected to the cells.
An example of SDF file can be downloaded here