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A netlist is a textual description of a circuit made of components.
Components are generally gates, so generally a Netlist is a connection
of gates. A netlist can also be a connection of resistors, capacitors or
transistors, which is a netlist when used in analog simulation tools
like spice. The scope of this site is limited to 'gate' level netlist only.
A netlist can be written by hand, but more generally its the output of
the process called synthesis. In this case the netlist then corresponds to
a description of a design written using a HDL when written in an RTL style.
The netlist is then supposed to perform the same function as the corresponding
HDL code.

The netlist out of the synthesis tool is then fed into layout tools to produce
the layout of the chip. During this process the netlist may be modified, but
remains functionally equal to its corresponding HDL code.
The netlist then written by the layout tool after the layout has been done
is often called post-layout-netlist.
The noticeable difference between the pre-layout-netlist and post-layout-netlist
is the inclusion of 'clock tree buffers' in the post-layout-netlist.

It is important to note that the layout tools are also capable of accepting
directly the HDL code as an input instead of a netlist which is produced
by synthesis tool. Which means that the layout tools can now perform
synthesis as well.

The popular languages used to write a netlist are:
An example verilog netlist can be downloaded here.

Related terms:

Formal Verificaion
RTL style of coding
Dynamic Simulation
Back Annotation