Synthesis is a process of converting an RTL code to a meaningful connection
of logic gates from a technology library. These connection of gates is formally
called a netlist. Such a netlist is supposed to realiaze the funtionality written in
the corresponding
RTL using logic gates.

It is just an automatic process to convert a description written in HDL to make
a gate-level equivalent circuit. This automatic process is carried out by
what are called synthesis tools, which are softwares available from major
EDA vendors like Synopsys, Cadence or Mentor Graphics.

Leading EDA vendors like Synopsys, Cadence, Mentor Graphics offer tools
which can perform synthesis.
The input to the synthesis tool is a RTL description, a library of gates, often
called a technology library and a set of constraints. The output of a synthesis
tool is a gate level netlist
Design Compiler is one of the most popular Synthesis Tools

Related Terms:
Formal Verification