RTL stands for Register Transfer Language. It is a coding style to code
Designs, so that a Synthesis tool may be able to read it and convert it into
'gates' or what is formally called a netlist.
VHDL and Verilog are 2 HDL languages used to describe the design in RTL style.
A small RTL code of a counter can be downloaded here.

Not every code written using HDL (vhdl or verilog) is synthesizeable.
Normally RTL refers to the code which is synthesizeable. That is the code
which can be successfully converted into a functionally equivalent netlist
by commonly available synthesis tools such as design compiler from synopsys

RTL design is one of the most important steps in ASIC design, where some form of
Specification is converted manually into machine read-able description or model,
which is called RTL code, which then can be subjected to various automation steps
to make a chip out of it. At present writing, various attempts in the industry are
going on, to generate RTL automatically from a C language model, or a
systemC language model or a SystemVerilog model.

Related Terms:

Formal Verification