Static Timing Analysis:

One of the most important characteristic of a digital design is its operating
frequency. The operating frequency of a design is the frequency of the clock it
is capable of working at*. While a chip has to be verified functionally before
going into production, it must also be verified that it can work on the
specified clock frequency(Apart from other verifications which also must be done)
While 'simulation' is the way to verify the
functionality of the chip before production, Static Timing Analysis is the
way to verify the timing or the frequency of operation of the chip/design
before production.
Since there is no simulation involved in this analysis, it is considered
to be 'static', and hence the name 'Static Timing Analysis'

Consider this circuit:

The circuit shows a 3 bit counter. It works on a clock 'Clk' shown, and it counts when
'count_enable' is '1', and it preserves the current count when 'count_enable' is '0'. A
rst_n input port is used to reset the count value synchronously before start.

The problem here is to find out if this design will work with the clock
having a frequency 'f'

If the frequency of the clk is f, i.e the time period is 1/f, say T,then in
order for the above circuit to work, the time taken by the signal from Q to D
must be less than or equal to T-tsetup**, i.e
tclk->q + tadder + tmux + tand  <= T - tsetup
tclk->q + tadder + tmux + tand + tsetup <= T
tclk->q + tcombi + tsetup <= T, where tcombi = tadder + tmux + tand
So if we have the values of these variables, then we can say if the given circuit
will or will not work at a clock with the frequency 'f'.
The above analysis of determining weather a given design will or will not
work at a given frequency is precisely what is called as 'Static Timing Analysis'

The inputs of STA are:
1. Design i.e a netlist
2. Constraints, i.e frequency of clock, the delay values of input signal
count_enable and rst_n with respect to clock edge,
3. The delay values of the gates in the netlist.

The output being a report, telling if there are any paths which are failing.

The longest timing path in the design is called 'Critical Path'.

Synopsys' Prime Time is one of the EDA tools used to perform STA

Also see:
Critical Path
Setup Time
Hold Time

*It must be noted that a design may consist of several sub designs or 'blocks'
working at different clock frequencies.To make the understanding simpler, it
is assumed here that the design is working off a single clock source.

**It is being assumed that the delay of the input signals 'rst_n' and 'count_enable'
with respect to 'Clk' are less as compared to tcombi . And special effects such as
clock uncertainty, clock skew are being ignored.