UVM e Verification Tutorial using Specman
2. Transactional Level Modelling (TLM)
Its important to first understand what is TLM or transactional Level
The name for sure sounds intimidating, but the concept is really
simple. And this is what the UVM/OVM
concepts are based upon. if you already know what is TLM, you may
want to skip this section.
Once upon a time, in Silicon Valley, we used to write testbenches,
which used to drive each and every signal of
the DUT, with the stimulus specified for each input at each clock
Now, of course we dont do that.
What we do is, we define what is called a 'data item'. This is the
'unit' of stimulus which the UVM/OVM
testbench generates or will generate upon command or upon request.
So TLM does not generate individual signals at individual clock
cycles, TLM means a method to generate
a 'data item' and drive the same as stimulus to the DUT or DUT
Heyyyy... but what is TLM.
Its the way of modelling a testbench which generates a 'data item'
instead of individual stimulus for each input
on the DUT or a specific interface of DUT, which is under test is
Heyyyyy... but what is a 'data item'.
A Data Item is the smallest Unit produced by TLM testbench or TLM
Example 1 : Data Item.
Following is an example of a 'data item' written in 'e' language.
The 'avi_ahb_if_tran' is a 'struct' type which is 'like inherited
from a pre defined 'e' type called 'any_sequence_item'
This data item has many 'fields' for example, 'haddr' is a field
which is of type 'haddr_t',
'htrans' is a field of type 'htrans_t', 'hsize' is a field of the
pre-defined type 'unsigned integer' (uint) and its 3 bits wide
... and so on and so forth.
struct avi_ahb_if_tran like
%haddr : haddr_t;
%htrans : htrans_t;
%hwrite : uint (bits : 1);
%hsize : uint (bits :
%hburst : hburst_t;
%hprot : uint (bits :
%hwdata_l : list of hwdata_t;
!%hrdata : hrdata_t;
!%hrdata_l : list of hrdata_t;
!%hready : uint(bits:1);
!%hresp : uint(bits:2);
%hbusreqx : uint (bits :1);
%hlockx : uint (bits :1);
The name 'avi_ahb_if_tran' is user defined, its the name that is
given to a new 'struct'.
'like inheritance': This means that 'avi_ahb_if_tran' is a 'struct'
which has all the properties of
the predefined struct 'any_sequence_item'.
'any_sequence_item' : This is a predefined struct available in the
All data items must be defined as 'like inherited' from the
base type 'any_sequence_item'. Why?
Because this is the rule of UVM. :).
As perviously discussed, UVM is a standard way of coding your
and if you have to follow this standard, you got to follow its
rules. :) Simple!.
Getting bothered by the signs '!' or '%' before the 'fields' of the
struct. Find an explanation here.