UVM e Verification Tutorial using Specman by Aviral Mittal.

I had a bit of difficulty in finding out how does a generated data item is driven to the HDL in UVM e verification environment.
But eventually I was able to find it out. So I prepared a conceptual diagram encapsulating the vital
information that I collected through a painful method. I hope ppl will find it useful.

All the *fields in the diagram such as *agent, *driver are the e-pointers to specific objects. This is not
e-syntax, its just symbolic so that ppl can understand.
All the items in box are instances of units or structs.

Bit of explanation:

The following diagram shows the UVM verification env from the hierarchial perspective.

A seq_item is a basic object which is like inherited from 'any_sequence_item'
This is automatically generated by the 'driver's' 'run()' method, which in turns generates 'sequence'.
This seq_item is retrieved by the bfm, when the bfm calls driver's 'gen_next_item()' method.
The required fields from this seq_item are then assigned to 'ports' type inside the BFM.
the BFM then sends the fields of seq_item to what is called a 'signal map' which in turn drives these fields to actual HDL signals.

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Key words : Verisity Specman e Tutorial. Specman e Introduction.