VLSI IP

HufGen
Its a tool to generate synthesizeable VHDL code to   
decode huffman bit string. The input to the tool is a
huffman table, and the output is the RTL. It also
generates a testbench to verify the RTL produced by
the tool. It works on Unix/Linux platform.
Click here to get HufGen document.
Click here to download a HufGen Produced RTL and
testbench