VLSI IP
Welcome to VLSI IP : Owned by Aviral Mittal
ASIC/VLSI Design Info
ASIC/VLSI Design Tutorials
Free IPs
VLSI/ASIC Interview Questions VLSI/ASIC Dictionary(Under Construction)
VHDL PAGE
Sample Verilog Codes
Modelsim Notes
Unix/Linux Notes
Planning to Study VLSI/Microelectronics in UK?
Specman 'e' UVM Tutorial
MS Excel TIPS
ARM AMBA AXI AHB INFO
Synopsys Core Assembler Tutorial
OVM/UVM SystemVerilog Tutorial
SoC System On Chip Design/Arch Tutorial
ARM Cortex M4 Power Management Tutorial
AXI vs AHB or AHB vs AXI : How does AXI provides more performance than AHB
Blue Tooth Random Info
SoC Security Fundamentals
Embedded C Fundamentals
Keil uVision5 Basic Tutorial
Cortex-M0 Info
Cortex-M3 Integration Guide
Design And Build Your Own SoC using ARM Cortex-M3. System On Chip Design Course/Tutorial
Xilinx Vivado System-on-Chip Design Basic Tutorial
Decoding Keil startup.s assembler code.(For ARM Cortex-M Processors)
Getting Started ARM Cortex-M33 TZ (TrustZone). Secure to Non-Secure Switch using BLXNS instruction. C/Assembly code.
AMBA(AXI/AHB) WRAP Brust/WRAPPING Brust type
What is XIP Execute in Place
SoC Security Fundamentals -PART II Root of Trust
What is ARM Privilege/User Mode (Cortex- M)
What is ARM Trust Zone (Cortex- M)
What is Scatter-Loading (ARM Cortex-M)
Example Scatter-Loading File with Explanation(ARM Cortex-M)
Scatter-Loading : A Practical Exercise.(ARM Cortex-M)
SoC Architecture/Design Tutorial -2
Which ARM Cortex-M processor; Selecting the right Cortex-M for your SoC
Arm Cortex-M Comparing the Privileged/Non-Privileged and Secure/Non-Secure
Arm Cortex-M MPU Memory Protection Unit
Cache Memory Tutorial
What is Virtual Memory
Different Clock Sources on a Small SoC XTAL, PLL, RCO
CHI vs MOESI Cache coherency protocols
The Cache Coherence Directory
Synthesizable Verilog Modules:Verilog Lego :)
Silicon Worthy Verilog ASYNC FIFO Module (No Commercial use permitted)
My Tennis Hobby Site
