Xilinx Vivado Tutorial: Build your own System on Chip Design.
Firstly, the user will create a new project in Vivado
The user will then add all the RTL files to the project
The user will then run a basic synthesis
The user will then run Elaboration
The user will then write a small testbench and add the same to the project
The user will then run Simulation
Step 1. Creating a Project:
After downloading And installing Xilinx Vivado, Click on the Vivado
icon to launch Vivado
Following Window will open:
A new Project will now be created: Click on Quick Start -> Create
Project >
Following Window will show up
Click on Next >
Following window will show-up asking for the user to fill in
'Project Name' and 'Project Location'
You can choose any name of the project, here the project name is
chosen to be 'soc_cm3'
Choose a working directory, here it is 'C:/Users/<windows user
name>/downloads/asic_design/xilinx'
Click on Next >
Following window will shop up, asking for the user to put in 'Project
Type'
Select 'RTL Project' from the list as shown below:
Click on Next >
'Add Sources' Window will show up asking the user to add project
files as shown below:
Click on 'Add Files' , 'Add source Files' window will show up as
shown below:
Browse to the directory where your source files are:
Your Bus Matrix files should be here: asic_design/xilinx/cortexm3_soc/cm3_matrix/rtl
Browse to this directory, and select all files as shown below and
click on OK.
Similarly add the following files, by clicking on 'Add Files' again
and repeating the process:
Ignore the 'work' directory as seen above, you may not even see it.
All files have now been added. Click on Next >
Add Constraints Window will Show up, Ignore it for the moment and
click on Next >
'Default Part' Selection Window will show up, select the following:
Family -> Artix-7
Speed -> -1
Rest keep as they are:
Then select the part called xc7a100tcsg324-1
All this is shown below:
Click on Next >
'New Project Summary Window will show up' as shown, click on
'Finish'
A few moments later the project creation step will conclude and the
user will be able to see their project listed in Vivado's 'PROJECT
MANAGER' pane as shown below:
Step 2 : Run Synthesis:
Now Click on 'Run Synthesis'
Launch Runs window will show-up, Click on OK
Synthesis will take time (5-10 mins): The user will see a small
green activity circle rotating 'Running synth_design', telling that
the synthesis is going on, as shown below:
Synthesis Completed Window will then show up, asking 'Next' actions
'Run Implementation', 'Open Synthesized Design', 'View Reports'.
Ignore it, click 'Cancel'
There can be 100s of warnings, ignore them as well.
Step 3. Elaborate and View Schematics:
Click on 'Open Elaborated Design'
Some message might pop-up, ignore it.
Elaboration will then start, and it will take time to finish.
The user will be able to see their design Schematics in the Tool
Window.
Step 4: Run Simulation:
Before the user may run a simulation, the user will need a
test-bench file and a 'binary/hex' corresponding to the small C +
Assembly code written. Section
4 of this tutorial explains how to create this 'image.hex'
file, needed by simulation. A
cheat 'image.hex' file is provided here.
The testbench file is shown below: module
cortexm3_soc_tb;
reg HCLK;
reg HRESETn;
initial begin
HCLK = 0;
HRESETn = 0;
endmodule
Copy this file and save it as 'cortexm3_soc_tb.v'. in the 'asic_design/xilinx/cortexm3_soc/top/tb'
directory. (you may have to create the 'tb'
directory)
Then add this testbench file using 'Add Sources' , and then browsing
to the above directory.
The user may see a message in a yellow bar at top
'Elaborated Design is out-of-date. Design sources were modified
details Reload'
Click on Reload
Elaboration will start again, it will take time
After elaboration will finish, you will see the 'cortexm3_soc_tb'
at the top of your design hierarchy. The schematic will also change
Edit the 'asic_design/xilinx/cmsdk_fpga_sram/verilog/cmsdk_fpga_sram.v'
file and comment out line numbers 90 (`ifdef
SIMULATION=> //`ifdef SIMULATION)
and and 119 (`end if //SIMULATION => //`end
if //SIMULATION)
Click on Run Simulation -> Run
Behavioural
Simulation.(this option show up in a pop-up menu when the
user clicks on 'Run Simulation'
This will again take time
The user will be able to see a waveform window in the tool:
Go in the 'Black Region' of the waveform window and Right Click
-> Full View
Browse the design pane to go to 'cortex_m3_soc'
then in 'Objects' pane, click on 'lens' icon (search icon), a small
input box will open, write 'HADDR' in it. Then select 'HADDRI' ,
'HADDRD' and 'HADDRS' and drag them to the Black Waveform pane to
add these to waveform window:
Since nothing can be seen in HADDRs, the Simulation needs to
restarted:
To Restart the Simulation: Click on Window -> Tcl Console. This
will open up a small command window at the bottom of the Tool.
Type in the command 'restart' prese enter.
Type in the command 'run 10000' press enter.
The user will see all the HADDRs are going Red 'Xs'. This is because
the 'image.hex'
file needs to be copied to the following simulation directory. asic_design/xilinx/soc_cm3/soc_cm3.sim/sim_1/behav/xsim
After copying the 'image.hex' file into the above directory, restart
the simulation again by issuing the following commands again int the
'Tcl Command' box
restart
run 10000
The user will be able to observe good waveforms now.
The user will observe that the HADDRI is the first address to show
an address of 0x0000_0000, then 0x0000_0004 etc.
Congratulations to the User. The user has just run their own
software on their own SoC.
This concludes the 'Stage1' of the SoC design Web Course.
Keep checking this site for 'Stage2'
