SITE HOME
Section 5:
This section deals with the RTL Simulation of the Tutorial.
The Simulation is done using 1. Synopsys VCS, 2. Xilinx Vivado (Free).
This section is on Synopsys VCS, for Xilinx, Click on Next at the bottom of this page
The VCS script is presented here:
Vcs -debug_all -sverilog
-override_timescale=1ps/1ps\
+incdir+../cortexm3_soc/cmsdk_fpga_sram/verilog\
+define+SIMULATION\
-f list.txt
./simv -gui
Put all the above in a file say vcs.scr and
then
source vcs.scr
Where the file list.txt contains the file names with either relative
(to the directory where you are running your simulations) or full
paths.
It is recommended that the simulations are run in the following
directory:
asic_design/xilinx/cortexm3_soc_sim
(You will have to create this directory).
Very Important: It is very important
that the 'image.hex' file generated in the previous Section, i.e.
Section 3, must be placed inside the simulation directory
otherwise nothing will work.
When the VCS loads up, run for 10000 time units, i.e run 10000
Here is a screenshot of the simulation:
SITE HOME
Click Here to Make
Comments:
<=
Back to Section 4
Next to
Section 6 (Run RTL Simulations, using Xilinx Vivado.
=>