OVM/UVM: A Practical Tutorial Using System Verilog
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-Aviral Mittal

UVM Testbench:

What is a UVM testbench:
UVM testbench  or more appropriately a test environment
may be defined as verification infrastructure coded using SystemVerilog using what is called
UVM class library, in a way that it follows a pre-defined 'standard'. This pre-defined standard
will dictate what components the test env itself will have, and their hierarchy and their interaction etc.

UVM class library is a library of SystemVerilog 'classes' available free of charge,
as it is an open standard developed by leading EDA companies.
We will use these available UVM 'classes' to build a UVM compliant testbench.

In summary,
The Unit of stimulus (sequence item) is generated on demand by UVM testbench, the field values of the generated
'sequence item', for example 'hburst' or 'haddr' etc are mapped to the corresponding fields of the 'Interface', 
the interface fields then map (or connected) to the DUT signals, and that's how the DUT's signals are wiggled.

The UVM tesbench would help you to generate constrained-random stimulus, and would help you to drive this
stimulus to DUT, then it will help you to capture the response from the DUT, and it will also
help you to automate the response checking.

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KeyWords: OVM, UVM, SystemVerilog, Constrained Random Verification, Transaction Level Modelling.