AXI : AMBA AXI Infomation by Aviral Mittal avimit att yahoo daat com.
Date : 19 April 2014.

Random information about AXI.

About Memory Attributes

AXI3 Vs AXI4, Difference between AXI3 and AXI4

For AHB click here

Section A5.1 says
"By using AXI IDs, a master can issue transactions without waiting for earlier transactions to complete".
Then Section A3.2.2 says
"When asserted, AWVALID must remain asserted until the rising clock edge after the slave asserts AWREADY".

Can someone explain how these two are possible? Say for example, the slave doesn't assert AWREADY?
In this case, can the master sill issue transactions without waiting for earlier transactions to complete? I DONT think so!!!

Only one command on one channel(read/write/write data/read data/cmpl) may be issued at a time. Unless this command
is accepted by the Slave, No command on the same channel may be issued, with or without AXI ID?

Here is an example what this actually means:
If a master wants 2 kinds of data, and if there were no ID facility in AXI, then the master would not be able to issue
say read transactions in a read,read,read,read fashion, without worrying about the return data. i.e. the Master would
not be able to pipeline reads to facilitate continuous data stream. This is because, the master would have no way
to identify which return data belongs to which 'kind'. however by attaching ID the master can issue
read0,read1,read0,read0,read1, and pipeline the 2 kinds of data to form a continuous read data stream.
When the data comes back it will have a ID which will identify the data as of kind0 or kind1.
The two kinds of data can be say, 'data descriptor fetch' and 'data fetch'.

Q: Why does AXI has separate response channel for Writes and Not for Reads?
Write has 3 channels
1. Write Address.
2. Write Data
3. Write Response.

While the write address and write data channel are in same directions,
The read address and read data channel are in opposite directions.

There needs to be a mechanism where a response is required back from the destination.
In case of read, the response can be the data, but it is actually the response that follows
the data on the same read channel, which comes from the destination
In case of write, there is NO data flow from destination to source if there was no response channel

Now since the response always follows the data, the response channel in case of read is the
same as data channel
But in case of write, the response channel has to be separate as the ONLY channel from destination to source.

Relation between Write Address and Write Data channels:
Write address and write data channels must be presented to slave at the same time. I.e the address and data
must be aligned or re-aligned (by the interconnect i.e by the fabric). This means that the write address
and write data channel cannot be independent. This is because the address identifies the slave. If the write
address and write data channels are not in sync, then the slave will NOT receive the address and corresponding

Once VALID signal is asserted, it must remain asserted until the handshake occurs, at a rising clock edge at which
VALID and READY are both asserted.
If READY is asserted, the destination is permitted to de-assert the READY signal before VALID is asserted.

Even if a slave has only one source of read-data, it must assert the RVALID signal only in response to a request for data.

For a write transaction, a single response is signaled for the entire burst, and not for each data transfer within the burst.
While, in a read tran, the slave can signal diff responses for different xfers in a burst. For example, in a burst of 16 read
xfers, the slave might return an OKAY response for 15 of the transfers and a SLVERR response for one of the xfers.

Slaves are required to reflect on the appropriate BID or RID respons an AXI ID received from a master.

The interconnect appends additional bits to the ARID, AWID and WID identifiers that are unique to that master port.
This means:
1). A masters on a fabric need not worry about what ID the other masters(s) would use, as the ID will be uniquified by
the fabric
2). ID width at slave will be larger than the ID width at Master.

A AXI4 Master(i.e. without any WID signal in its write data channel), MUST issue the write data
 "in the same order in which it issues the transaction addresses".

The slave must ensure that the RID value of any returned data matches the ARID value of the address to which it
is responding.

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