Ever wondered how to estimate power of your design: Its relatively simple:

This tutorial takes a simple binary counter as a design, and performs power analysis on it using Synopsys' Design Compiler.
What you will need is:
1. The design:
The RTL of the counter can be downloaded Here: (RTL is not used in the flow and
is given for information only, you may want to take it and synthesize it to your own netlist
using the tech libs available to you)
The synthesized design i.e Netlist(Verilog) can be downloaded Here:
The corresponding ddc of the synthesized design can be downloaded Here:
The synthesis script can be downloaded Here:
 

3. A Testbench
To simulate the design and produce a 'Activity' file. This activity file is a
record of transitions each net underwent during simulation. Since transitions affect dynamic
power, the activity file is a very critical input into power estimation.
A Testbench can be downloaded Here:

3. VCD file: Output of the simlation containg simulation data
An example of the vcd file used can be downloaded Here:
If you are using NC-Sim, you may dump a vcd file using the following command
database -vcd T0001
probe -depth all -all
run 100 us
exit

Steps:
#1. Convert the vcd file into 'saif' format using
vcd2saif -input T0001.vcd -o T0001.saif
Note: vcd2sail is provided by synopsys. So if you have design compiler running on
a unix shell, 'vcd2saif' should work as well. An example saif file can be downloaded Here

#2. Invoke design compiler in tcl mode
dc_shell-t
On dc_shell prompt
set search_path {/homes/amittal/s5/work/physical_lib/corelib/tsmc_090_g_art}
set target_library {scadv_tsmc_cln90g_lvt_ss_0p9v_125c.db}
read_ddc binary_counter.ddc
read_saif -input T0001.saif -instance_name binary_counter_tb/binary_counter_u1 -verbose
report_power > power.rpt
exit

That's it. The output power.rpt contains the power consumption figure.
Note that the instance name used in 'read_saif' command above is given with the full path.
This is very important for successfull annotation of saif.

It is important to note that:
1.
You may see warnings about the nets not being properly annotated. If these nets are internal nets of
the cells of the techology library, then these warnings can be safely ignored. If not, then the annotation
is unsuccessfull. Here is a copy of the warnings which were produced in this design. These were
safely ignored. As you may note that these warnings are all referring to internodes of cells form
a tech lib.

Other problems may look s'thing like:
(a) Error: No switching activity has been annotated
This usually means that the saif annotation has not been successfull. Problem may lie in the
instance name used in 'read_saif' command.

2.
It is important to read design 'ddc' and not the design 'netlist' for power analysis. This is because
the 'ddc' is expected to contain the clock information, the input slopes, ouput loads which all influence
the power consumption.

3.
The simulation should be run for sufficient amount of time, using a testbench which resulted
in exercising the design to its limit.

4.
You can also dump a vcd file out of your RTL simulations, and then annotate it during power
analysis. This will indicate how much difference is between the power analysis when
a). RTL activity file is annotated on netlist( less accuracy, but avoids lengthy netlist simulations)
b). netlist activity file is annotated on nelist (more accuracy)

Other power estimation tools:
PowerTheatre: is a power analysis tools which clamis to perform power analysis using RTL and
RTL activity file. They claim that the results obtained are in 10% accuracy of Netlist power
estimation results. The vendor offering this tool is 'Sequence Design Automation'

Koi shak ya sawal?
avimit at yahoo dat com