needs to be verified before it is sent for production.
To verify the design, it is given a set of inputs, the response
of the design/circuit is observed, and is compared against the
expected response to determine if the design/circuit under test
is functionally correct.
This process of testing/verifying a design is called Simulation.
In ASIC design world, a design is usually an HDL model written
using modeling languages such as SystemC or SystemVerilog or a
model written using HDL such as VHDL or Verilog
The inputs are given to the design using another model written
in either languages mentioned above, which is usually called
A simulation tool such as modelsim, is then used to
1. Compile the design
2. Compile the testbench
3. Simulate the design with the inputs generated by testbench
Consider an example of a simple counter shown here.
The counter can be reset to '0' by using a synchronous input 'rst_n'
The counter counts when 'count_enable' is '1', and preserves the
count value when the signal 'count_enable' is '0'.
The vhdl model of this counter can be downloaded here
The vhdl model of the testbench can be downloaded here.
A simulation plot, i.e the waveform plot can be seen here:
To run simulation on the downloaded file(s) using modelsim:
1. make a library using vlib command where modelsim will keep the
2. Compile the design in the above library
vcom -work my_work counter.vhd
3. Compile the test bench in the above library
vcom -work my_work counter.tb.vhdl
4. Issue the simulate command.
This will open a modelsim window
5. plot waveforms to observe(use the following commands in modelsim
add wave sim:/counter_i0/Clk
add wave sim:/counter_i0/rst_n
add wave sim:/counter_i0/count_out
6. Run Simulation:
run 200 ns
7. Quit Modelsim if you so wish
The values given to the input ports of a design by a test bench
in each clock period is often called as 'test vectors'
Static Timing Analysis