Synopsys Design Compiler A quick Tutorial:
Connect @
-Aviral Mittal
Download commad script for this tutorial here
Downlaod vhdl source code(s) for this tutorial
counter_top.vhd here
counter.vhd here
Download resulting netlist on tsmc lib here

Step 0. Invoke Design Compiler
            unix> dc_shell-t

Step 1. Setup technology library. To synthesize a design you need technology library which will contain
       description of the cells from the fab, and their timing. This is usually a .db file found in
       library installation directory. To do this
     1(a). Tell synopsys where your <library>.db file is.
set search_path {/homes/amittal/s5/work/physical_lib/corelib/tsmc_090_g_art}
     1(b). Tell synopsys what is your technology library, which you want to map your design on called
set target_library {scadv_tsmc_cln90g_lvt_ss_0p9v_125c.db}
     1(c). Set up link libraries. This is optional .db files which are pre synthesized and ready to be read in
     For this, append your search path where your optional .db files are
lappend search_path {[exec pwd]}
           lappend search_path {.}
     1(d). Set up link libraries. This is optional .db files which are pre synthesized and ready to be read in
set link_library  {PLL10CCMID_W_125_1.35.db}
Step 2. Read In your design files
     2(a). if it is verilog:
       read_verilog counter.v
     2(b). if it is vhdl: As it is in this tutorial
read_vhdl counter.vhd
read_vhdl counter_top.vhd
     2(c). if it is ddc:
read_ddc counter.ddc
Step 3. Set Design Constraints:
     3(a) Set frequency of operation: You have to create a clock in the design,
     With a given timeperiod. The command below creates a clock and calls it
     'design_clk' with a timeperiod of 10 ns, (100MHz), and maps it to the
      'clk' input of the design.
create_clock -period 10 -name design_clk clk
     3(b) Set input constraints : Set how much time would be spent by
     signals arriving into your design, outside your design with respect to the clock
set_input_delay 4.0 [remove_from_collection [all_inputs ] clk] -clock design_clk
     3(c) Set output constraints : Set how much time would be spent by
     signals leaving your desing, outside your design, before they are captured by
     the same clock
set_output_delay 7.0 [all_outputs] -clock design_clk
     3(d) Set area constraints : set maximum allowed area to 0 :). well its just to
     instruct design compiler that use as less area as possible.
set_max_area 0
Step 4. Enable clock gating for low power (optional)
     4(a) The following commands will try to insert clock gates for each 2 registers
set_clock_gating_style -minimum_bitwidth 2
Step 5. Write formal verification setupfile (optional)
set_svf -append "counter.svf"

Step 6: Set Operating Conditions
set_operating_conditions \
        -analysis_type on_chip_variation \
        -max_library tcbn65lpwc_ccs \
        -max WCCOM \
        -min_library tcbn65lpwc_ccs \
        -min WCCOM
Step 7: Set Timing Derating. This is to compensate for variation on the timing paths on actual silicon.
set_timing_derate -min -late  1.05
set_timing_derate -min -early 1.00

Step 8: Set clock uncertainity, this is done to offset the expected clock skew.
set_clock_uncertainty -setup 0.500 [all_clocks]
set_clock_uncertainty -hold  0.000 [all_clocks]

Step 9 : Set driving cell on inputs
set_driving_cell  -lib_cell DFD1  -mult 1.0 -library tcbn65lpwc_ccs -pin Q [remove_from_collection [all_inputs] [collection_to_list [get_clocks]]]

Step 10: Set load on all outpus
set_load [expr 2 * [load_of [get_pin tcbn65lpwc_ccs/INVD4/I]]] [all_outputs]

Step 11: If needed set dont use on certain lib cells
set_dont_use [get_lib_cell  tcbn65lphvtwc_ccs/*DEL*]

Setp 12: Set maximum trasition limit
set_max_transition 0.500 [current_design]

Step 13: Group Certain paths: It is always a good idea to group certain paths together to help better optimisation of paths
Synopsys by default works on worst paths. In absence of groups it will work on the worst path, that may or may not be
what is desired. Grouping paths will force design compiler to work individually on worst paths in each group.
set ports_clock_root [get_ports [all_fanout -flat -clock_tree -level 0]]
group_path -name INP_PATHS -from [remove_from_collection [all_inputs] $ports_clock_root] -critical_range 10.0

Step 14. Set Register optimization veriables (optional)
     (a) Set automatic removal of constant flipflop(s)
set compile_seqmap_propagate_constants true
     (b) Set automatic removal of unloaded flipflop(s)
           set compile_delete_unloaded_sequential_cells false
Step 15. Set mapping of sync resets to aviod Xs in sims (optional)
set hdlin_ff_always_sync_set_reset "true"
Step 16. Set the name of top level as current design and compile the design
     (a) current_design counter_top
compile -map_effort high
     (b) If you are using dc ultra :
           You may want to turn off output inversion of sequential cells
compile_ultra -no_seq_output_inversion
Step 17. Write design output netlist
     17(a).Write output in ddc format
write -format ddc -output counter.ddc -hier
     17(b).Write output in verilog format
write -format ddc -output counter.vlog -hier
Step 18. You may want to flatten your design before writing out netlist
ungroup -all -flatten
write -format verilog -output counter_flat.vlog
Step 19. Writing a timing report of your design
report_timing > counter_timing.rep
Step 20. Quit Design Compiler

More random DC shell Tcl mode Commands:

define_design_lib lib1 -path ~/misc/vhdl
analyze -library lib1 -format vhdl /homes/amittal/misc/vhdl/xx.vhdl
get_design_lib_path SYNTH
get_design_lib_path work

read_verilog mse.v

report_timing -delay max -from ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3] -to pCacheMemReqFifoDataOut

report_timing -delay max -through  [find net ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3]]

report_constraint -verbose -all_violators

create_clock -name "myclk" -period 13 [get_ports pClk]

set_output_delay 1.0 -clock [get_clocks myclk]  pCacheMemReqFifoDataOut[161]

set_wire_load_mode segmented

set_wire_load_mode enclosed


report_timing -from [find pin ARRAYCACHE_I/LatencyReqReg*/Q] -to pCacheMemReqFifoDataOut

report_timing -from [find pin ARRAYCACHE_I/CACHE_DATA_RAM/DO*] -to pCacheMemReqFifoDataOut

set_output_delay 1.0 -clock myclk pCacheMemReqFifoDataOut

set_false_path -through [find pin ARRAYCACHE_I/FracSetReg*/*]index

It is to be noted that if there are no constraints, 'set_false_path' does not actually works.

I tried to find delays to a output port, without any constraints, form a known point in the design.
I got that.
Then I wanted to find next worst path to that output port, to I set a false path on the path found above.
But it wouldn't work
I then created a clcok and constrainted the output port,
!! False path worked.... magic :)

create_clock -period 4.8 -name vclk
set_input_delay 2.5 pDmaReadRegIndex -clock vclk -add_delay
set_output_delay 2.5 pInsertNopOut -clock vclk -add_delay
set_false_path -from vclk -to PESWITCH_pClk
set_false_path -from PESWITCH_pClk -to vclk
set_false_path -from PESWITCH_pClk -through pDmaReadRegIndex -to pInsertNopOut
report_timing -from pDmaReadRegIndex -to pInsertNopOut

set_input_delay [expr 0.35*$vclk_period] [all_inputs] -clock vclk -add_delay
set_output_delay [expr 0.35*$vclk_period] [all_outputs] -clock vclk -add_delay
set_false_path -from PESWITCH_pClk -through [all_inputs] -to [all_outputs]

set compile_log_format "%elap_time %area %wns %tns %drc %endpoint %group_path"
 get all registers.

report_cell [all_registers]

foreach_in_collection el [all_registers]
puts [get_object_name $el]

set file_handle [open my_file a]
foreach_in_collection $el [all_registers] {
set reg_name [get_object_name $el]
puts $file_handle $reg_name
close $file_handle
  Design Ware components synthesis

DW_minmax : Getting empty minmax module? Here is a solution

remove_design -all
lappend search_path "./src"
define_design_lib WORK -path "./icm_lib"
set synthetic_library [list /pkg/qct/software/synopsys/2016.03-SP5-4-T0328/libraries/syn/dw_foundation.sldb]
set_app_var target_library "/usr2/avimit/syn/ql20soc_r0hd_eln20_1.000v_tt_25c_cn_ccn_nfeol_nbeol.db"

set link_library "* dw_foundation.sldb"
source ./scripts/analyze.tcl

analyze -format verilog /pkg/qct/software/synopsys/2016.03-SP5-2/dw/examples/DW_minmax_func.v

elaborate top_cpu

report_area -hier -nosplit
To Change the Hierarchy Separator from 'dot' to 'slash'
define_name_rules no_dot -restricted "." -replacement_char "/"
change_names -rules no_dot -hierarchy